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Generate region standard compliance fixes #239
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I accidentally prevented attributes on conditional and loop generate construct. I'm going to fixing that before going out of draft. |
Apparently attributes on generate regions are allowed in Verilog 2001, but Verilog 2005 is not a superset of Verilog 2001 so I didn't notice it before reading both standards... So in the end it's better to parse it but not print it. |
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Ok, I think this is now correct. Only tests are left. EDIT: It is incorrect, the removed begin/end in if statements are actually useful for the dangling else problem. |
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Standard compliance fixes (Checked against Verilog 1995/2001/2005 and SystemVerilog 2017 A.4.2): Do not accept generate regions inside other generate regions Accept attributes on all generate items independently from where they appear Do not print lone semicolon in generate region Print a block in for generate to be compatible with Verilog 2001
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I just pushed some revisions that should preserve most of the intended changes while fixing the issues raised in the test cases. What do you think? |
I've read your changes. They solve what I was trying to solve, but correctly. |
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Thanks for spotting these issues! This was a helpful PR.
I realized that my changes actually break applying attributes to generate items, so I'll have to work on this further. I am considering adding a |
Standard compliance fixes (Checked against Verilog 1995/2001/2005 and SystemVerilog 2017 A.4.2):
Do not accept generate regions inside other generate regions; this is now forbidden
Do not print lone semicolon in generate region; this cannot be printed anymore
Print a block in
for
generate to be compatible with Verilog 2001EDIT: Verilog standard are complicated because the syntax of a standard does not cover everything from the previous standard.
EDIT2: Added comments to explain why begin/end blocks are added in
if
andfor
.