Allow generate region from every standard

Standard compliance fixes (Checked against Verilog 1995/2001/2005 and SystemVerilog 2017 A.4.2): Do not accept generate regions inside other generate regions Accept attributes on all generate items independently from where they appear Do not print alone semicolon in generate region Print a block in for generate to be compatible with Verilog 2001 Other improvement: Do not force the true branch of an if generate to be a block
zachjs · May 24, 2023 · 9f992cb · 9f992cb
1 parent 0a7b025
commit 9f992cb
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Showing 2 changed files with 28 additions and 28 deletions.
diff --git a/src/Language/SystemVerilog/AST/GenItem.hs b/src/Language/SystemVerilog/AST/GenItem.hs
@@ -36,21 +36,22 @@ instance Show GenItem where
         printf "case (%s)\n%s\nendcase" (show e) bodyStr
         where bodyStr = indent $ unlines' $ map showGenCase cs
     show (GenIf e a GenNull) = printf "if (%s) %s"          (show e) (showBareBlock a)
-    show (GenIf e a b      ) = printf "if (%s) %s\nelse %s" (show e) (showBlockedBranch a) (showBareBlock b)
+    show (GenIf e a b      ) = printf "if (%s) %s\nelse %s" (show e) (showBareBlock a) (showBareBlock b)
     show (GenFor (x1, e1) c (x2, o2, e2) s) =
         printf "for (%s = %s; %s; %s %s %s) %s"
             x1 (show e1)
             (show c)
             x2 (show o2) (show e2)
-            (showBareBlock s)
-    show (GenNull) = ";"
+            (showBlockedBranch s)
+    show (GenNull) = ""
     show (GenModuleItem item) = show item
 
 showBareBlock :: GenItem -> String
 showBareBlock (GenBlock x i) =
     printf "begin%s\n%s\nend"
         (if null x then "" else " : " ++ x)
         (indent $ show i)
+showBareBlock (GenNull) = ";"
 showBareBlock item = show item
 
 showBlockedBranch :: GenItem -> String

diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
@@ -693,29 +693,31 @@ ModuleItems :: { [ModuleItem] }
   : {- empty -}                    { [] }
   | ";" ModuleItems                { $2 }
   | MITrace ModuleItem ModuleItems { addMITrace $1 ($2 ++ $3) }
-
 ModuleItem :: { [ModuleItem] }
-  : NonGenerateModuleItem { $1 }
-  | ConditionalGenerateConstruct    { [Generate [$1]] }
-  | LoopGenerateConstruct           { [Generate [$1]] }
+  : NonGenerateModuleItem           { $1 }
+  | AttributeInstance ModuleItem    { map (addMIAttr $1) $2 }
   | "generate" GenItems endgenerate { [Generate $2] }
+NonGenerateModuleItemA :: { [ModuleItem] }
+  : NonGenerateModuleItem                    { $1 }
+  | AttributeInstance NonGenerateModuleItemA { map (addMIAttr $1) $2 }
+-- This item covers module instantiations and all declarations
 NonGenerateModuleItem :: { [ModuleItem] }
-  -- This item covers module instantiations and all declarations
-  : ModuleDeclTokens(";")                { parseDTsAsModuleItems $1 }
-  | ParameterDecl(";")                   { map (MIPackageItem . Decl) $1 }
-  | "defparam" LHSAsgns ";"              { map (uncurry Defparam) $2 }
-  | "assign" AssignOption LHSAsgns ";"   { map (uncurry $ Assign $2) $3 }
-  | AlwaysKW Stmt                        { [AlwaysC $1 $2] }
-  | "initial" Stmt                       { [Initial $2] }
-  | "final"   Stmt                       { [Final   $2] }
-  | "genvar" Identifiers ";"             { map Genvar $2 }
-  | "modport" ModportItems ";"           { map (uncurry Modport) $2 }
-  | NonDeclPackageItem                   { map MIPackageItem $1 }
-  | TaskOrFunction                       { [MIPackageItem $1] }
-  | NInputGateKW  NInputGates  ";"       { map (\(a, b, c, d) -> NInputGate  $1 a b c d) $2 }
-  | NOutputGateKW NOutputGates ";"       { map (\(a, b, c, d) -> NOutputGate $1 a b c d) $2 }
-  | AttributeInstance ModuleItem         { map (addMIAttr $1) $2 }
-  | AssertionItem                        { [AssertionItem $1] }
+  : ModuleDeclTokens(";")              { parseDTsAsModuleItems $1 }
+  | ParameterDecl(";")                 { map (MIPackageItem . Decl) $1 }
+  | "defparam" LHSAsgns ";"            { map (uncurry Defparam) $2 }
+  | "assign" AssignOption LHSAsgns ";" { map (uncurry $ Assign $2) $3 }
+  | AlwaysKW Stmt                      { [AlwaysC $1 $2] }
+  | "initial" Stmt                     { [Initial $2] }
+  | "final"   Stmt                     { [Final   $2] }
+  | "genvar" Identifiers ";"           { map Genvar $2 }
+  | "modport" ModportItems ";"         { map (uncurry Modport) $2 }
+  | NonDeclPackageItem                 { map MIPackageItem $1 }
+  | TaskOrFunction                     { [MIPackageItem $1] }
+  | NInputGateKW  NInputGates  ";"     { map (\(a, b, c, d) -> NInputGate  $1 a b c d) $2 }
+  | NOutputGateKW NOutputGates ";"     { map (\(a, b, c, d) -> NOutputGate $1 a b c d) $2 }
+  | AssertionItem                      { [AssertionItem $1] }
+  | ConditionalGenerateConstruct       { [Generate [$1]] }
+  | LoopGenerateConstruct              { [Generate [$1]] }
 
 AssignOption :: { AssignOption }
   : {- empty -}   { AssignOptionNone }
@@ -1447,11 +1449,8 @@ GenItems :: { [GenItem] }
   | GenItems GenItem { $1 ++ [$2] }
 
 GenItem :: { GenItem }
-  : MITrace GenBlock              { uncurry GenBlock $2 }
-  | MITrace NonGenerateModuleItem { genItemsToGenItem $ map GenModuleItem $ addMITrace $1 $2 }
-  | MITrace "generate" GenItems "endgenerate" { genItemsToGenItem $3 }
-  | MITrace ConditionalGenerateConstruct { $2 }
-  | MITrace LoopGenerateConstruct        { $2 }
+  : MITrace GenBlock               { uncurry GenBlock $2 }
+  | MITrace NonGenerateModuleItemA { genItemsToGenItem $ map GenModuleItem $ addMITrace $1 $2 }
 ConditionalGenerateConstruct :: { GenItem }
   : "if" "(" Expr ")" GenItemOrNull "else" GenItemOrNull { GenIf $3 $5 $7      }
   | "if" "(" Expr ")" GenItemOrNull %prec NoElse         { GenIf $3 $5 GenNull }