Fix invalid PCH error

src/main/scala/chiseltest/simulator/IcarusSimulator.scala

@@ -113,7 +113,9 @@ private object IcarusSimulator extends Simulator with LazyLogging {
     val success = ret.exitCode == 0 && os.exists(lib)
     assert(
       success,
-      s"failed to compiler VPI shared library for circuit ${topName} in work dir $compileDir\n" + cmd.mkString(" ")
+      s"failed to compiler VPI shared library for circuit ${topName} in work dir $compileDir\n" + Utils.quoteCmdArgs(
+        cmd
+      )
     )
     lib
   }
@@ -141,7 +143,7 @@ private object IcarusSimulator extends Simulator with LazyLogging {
     val ret = os.proc(cmd).call(cwd = os.pwd, check = false)
 
     val success = ret.exitCode == 0 && os.exists(os.pwd / simBinary)
-    assert(success, s"iverilog command failed on circuit ${topName} in work dir $targetDir\n" + cmd.mkString(" "))
+    assert(success, s"iverilog command failed on circuit ${topName} in work dir $targetDir\n" + Utils.quoteCmdArgs(cmd))
     Seq("vvp", simBinary.toString())
   }
 

src/main/scala/chiseltest/simulator/Utils.scala

@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chiseltest.simulator
+
+object Utils {
+  def quoteCmdArgs(cmd: Seq[String]): String = {
+    cmd.map(arg => if (arg.contains(" ")) s""""$arg"""" else arg).mkString(" ")
+  }
+}

src/main/scala/chiseltest/simulator/VerilatorSimulator.scala

@@ -5,6 +5,7 @@ package chiseltest.simulator
 import firrtl2._
 import firrtl2.annotations._
 import chiseltest.simulator.jna._
+import chiseltest.simulator.Utils.quoteCmdArgs
 
 case object VerilatorBackendAnnotation extends SimulatorAnnotation {
   override def getSimulator: Simulator = VerilatorSimulator
@@ -219,7 +220,7 @@ private object VerilatorSimulator extends Simulator {
   private def run(cmd: Seq[String], cwd: os.Path, verbose: Boolean): os.CommandResult = {
     if (verbose) {
       // print the command and pipe the output to stdout
-      println(cmd.mkString(" "))
+      println(quoteCmdArgs(cmd))
       os.proc(cmd)
         .call(cwd = cwd, stdout = os.ProcessOutput.Readlines(println), stderr = os.ProcessOutput.Readlines(println))
     } else {
@@ -228,12 +229,11 @@ private object VerilatorSimulator extends Simulator {
   }
 
   private def DefaultCFlags(topName: String) = List(
-    "-O1",
+    "-Os",
     "-DVL_USER_STOP",
     "-DVL_USER_FATAL",
     "-DVL_USER_FINISH", // this is required because we ant to overwrite the vl_finish function!
-    s"-DTOP_TYPE=V$topName",
-    s"-include V$topName.h"
+    s"-DTOP_TYPE=V$topName"
   )
 
   private def DefaultFlags(topName: String, verilatedDir: os.Path, cFlags: Seq[String], ldFlags: Seq[String]) = List(

src/main/scala/chiseltest/simulator/ipc/IPCSimulatorContext.scala

@@ -321,7 +321,7 @@ private[chiseltest] class IPCSimulatorContext(
 
   private def start(): Unit = {
     if (verbose)
-      println(s"""STARTING ${cmd.mkString(" ")}""")
+      println(s"""STARTING ${Utils.quoteCmdArgs(cmd)}""")
     mwhile(!recvOutputs) {}
     isRunning = true
   }
@@ -417,7 +417,7 @@ private[chiseltest] class IPCSimulatorContext(
 private object TesterProcess {
   def apply(cmd: Seq[String], logs: ArrayBuffer[String], verbose: Boolean): Process = {
     require(new java.io.File(cmd.head).exists, s"${cmd.head} doesn't exist")
-    val processBuilder = Process(cmd.mkString(" "))
+    val processBuilder = Process(Utils.quoteCmdArgs(cmd))
     // This makes everything written to stderr get added as lines to logs
     val processLogger = ProcessLogger(
       { str => if (verbose) println(str) },