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Merge latest changes #58

Merged
merged 89 commits into from
Mar 5, 2024
Merged

Merge latest changes #58

merged 89 commits into from
Mar 5, 2024

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PhilippvK
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@PhilippvK PhilippvK commented Mar 1, 2024 •
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Summary

Compatibility:

  • Move to LLVM18
  • Automatically detect version of target LLVM

Examples:

  • Add RV32P examples

Support:

  • Add backend and settings for custom legalizer options (GISel only)
  • Allow overriding default mattr
  • Allow adding/running user-provided test files

CDSL2LLVM/PatternGen:

  • LLVM18 fix
  • Support imm Operands
  • Refactor build (copy PatternGen to target llvm)

Passes:

  • Add Pass API (and cleanup Flow)

InjectMarkers:

  • Strip whitespace before/after patch
  • Support directory (recursive) file patches

@PhilippvK
experiments with RV32P
3a99a67
@PhilippvK
move to llvm 18
3d7af8b
@PhilippvK
add legalizer info to settings (WIP)
a202492
@PhilippvK
fix patterngen mattr
2a124c8
@PhilippvK
implement automatic lookup up llvm version
852cc05
@PhilippvK
minor fix
26ac012
@PhilippvK
filter_model: fix and implement missing major opcodes
c87f0aa
@PhilippvK
add insert markers patch for llvm 18
5f89324
@PhilippvK
add examples/cfg/riscv.yml
67d273e
@PhilippvK
add insert markers patch for llvm 18
d9dd74b
@PhilippvK
refactor pattern-gen flow (setup)
77bdd33
@PhilippvK
riscv_isa_info: llvm18 fix
54638b8
@PhilippvK
insert_markers_llvm18: fix typo
0ecbf08
@PhilippvK
add backend if legalizer settings
b32330b
@PhilippvK
update cdsl2llvm dependency branch
0c67a66
@PhilippvK
RV32P.core_desc: split sunpkd8xy into multiple instrs
eee3148
@PhilippvK
RV32P.core_desc: add GPR32Pair register alias (unused)
b4bb65a
@PhilippvK
RV32P.core_desc: try new zpfsoperand mechanic (for better register pa…
55f32b8 
…ir detection)
@PhilippvK
filter.yml: update
fb0c2f5
@PhilippvK
riscv.yml: update legalizer settings
222143c
@PhilippvK
demo.py: load test files
d0c9095
@PhilippvK
demo.py: fix
a303895
@PhilippvK
llvmir writer fix
78ec345
@PhilippvK
riscv_gisel_legalizer: fix
6444449
@PhilippvK
flow: support user-provided test files (#50)
c3ef953
@PhilippvK
flow: detect duplicate patches
808541e
@PhilippvK
flow: gmir fix
845a3d0
@PhilippvK
flow: refactor generate (skip/only)
1d91ee8
@PhilippvK
flow: support user-provided test files (#50)
af97dc7
@PhilippvK
default settings: fix typos
a301924
PhilippvK added 29 commits March 4, 2024 09:31
@PhilippvK
PassResult: add outputs field (unused)
84418db
@PhilippvK
passes: add PassFormat (unused)
b5be067
@PhilippvK
fixes
b28c17b
@PhilippvK
try to split pattern gen step into formats and patterns
c6d0d43
@PhilippvK
fix Example.core_desc
be629e7
@PhilippvK
update demo
5218135
@PhilippvK
patterngen fix
d62b338
@PhilippvK
update cdsl2llvm branch
b8430f0
@PhilippvK
allow (per-model) pass skipping via settings
2c1eff1
@PhilippvK
fixes for cleanup and export step
c593fa7
@PhilippvK
more fixes
6d39cb7
@PhilippvK
passes: implement multiprocessing depending on number of cpus
386a8ed
@PhilippvK
settings: avoid duplicated list items when merging
dc5ed75
@PhilippvK
update xcorev cdsl submodule
67a5a9c
@PhilippvK
update demo
86effd5
@PhilippvK
generate instr info
eb18cc0
@PhilippvK
support model specific overrides
d64ce00
@PhilippvK
ignore 2 xcvalu instrs whihc fail type infer during llvm-tblgen
b2fdfe2
@PhilippvK
generate instr info (fixes)
9b2c885
@PhilippvK
generate instr info (fixes)
94ec993
@PhilippvK
lint
c84e476
@PhilippvK
generate instr info (fixes)
659f7d8
@PhilippvK
add instr_info_notes
c40dd95
@PhilippvK
generate instr info (fixes)
d114f5e
@PhilippvK
update examples
1618895
@PhilippvK
fix
0241f63
@PhilippvK
cleanup
6152ec1
@PhilippvK
fix
6b4f4cd
@PhilippvK
lint
01dab0b
@PhilippvK PhilippvK merged commit 68f969f into main Mar 5, 2024
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@PhilippvK @thomasgoodfellow