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[AMD] Default to stream-pipeline-v2 #4665

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merged 3 commits into from
Sep 26, 2024
Merged

[AMD] Default to stream-pipeline-v2 #4665

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174c27b
[AMD] Default to stream-pipeline-v2
sjw36 Sep 6, 2024
c281634
* use num_stages for hip
sjw36 Sep 18, 2024
aa7444b
Merge branch 'main' into sjw/remove-old-pipeliner
antiagainst Sep 26, 2024
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5 changes: 4 additions & 1 deletion python/test/unit/language/test_core.py
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Original file line number Diff line number Diff line change
Expand Up @@ -5266,11 +5266,13 @@ def matmul_kernel( #
@pytest.mark.parametrize("in_type_str", ['float8e5', 'float8e4nv', 'float8e4b15'])
@pytest.mark.parametrize("low_precision_acc", [0, 32, 64, 128])
def test_dot_max_num_imprecise_acc(M, N, K, BLOCK_M, BLOCK_N, BLOCK_K, in_type_str, low_precision_acc, device):
num_stages = 3
if is_cuda():
cc = torch.cuda.get_device_capability()
if cc[0] >= 9 and in_type_str == "float8e4b15":
pytest.skip("Dot op does not support fp8e4b15 on CUDA arch >= 90")
elif is_hip():
num_stages = 2
if in_type_str != 'float8e5':
pytest.skip('test_fp8_dot_acc for HIP currently broken in upstream.')

Expand All @@ -5284,7 +5286,8 @@ def test_dot_max_num_imprecise_acc(M, N, K, BLOCK_M, BLOCK_N, BLOCK_K, in_type_s
grid = (triton.cdiv(M, BLOCK_M) * triton.cdiv(N, BLOCK_N), 1)
max_num_impressive_acc = low_precision_acc if low_precision_acc <= BLOCK_K else None
h = matmul_kernel[grid](a, b, C, M, N, K, a.stride(0), a.stride(1), b.stride(0), b.stride(1), C.stride(0),
C.stride(1), BLOCK_M, BLOCK_N, BLOCK_K, max_num_impressive_acc, num_warps=num_warps)
C.stride(1), BLOCK_M, BLOCK_N, BLOCK_K, max_num_impressive_acc, num_warps=num_warps,
num_pipeline_stages=num_stages)
torch_a = torch.from_numpy(A).to(device=device)
th_a = f8_to_f16(torch_a, in_type_str)
torch_b = torch.from_numpy(B).to(device=device)
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10 changes: 5 additions & 5 deletions python/tutorials/03-matrix-multiplication.py
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Expand Up @@ -206,19 +206,19 @@ def get_hip_autotune_config():
return [
triton.Config(
{'BLOCK_SIZE_M': 128, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 16, 'GROUP_SIZE_M': 1, 'waves_per_eu': 2},
num_warps=4, num_stages=0),
num_warps=4, num_stages=2),
triton.Config(
{'BLOCK_SIZE_M': 256, 'BLOCK_SIZE_N': 256, 'BLOCK_SIZE_K': 16, 'GROUP_SIZE_M': 4, 'waves_per_eu': 2},
num_warps=8, num_stages=0),
num_warps=8, num_stages=2),
triton.Config(
{'BLOCK_SIZE_M': 128, 'BLOCK_SIZE_N': 128, 'BLOCK_SIZE_K': 32, 'GROUP_SIZE_M': 1, 'waves_per_eu': 2},
num_warps=8, num_stages=0),
num_warps=8, num_stages=2),
triton.Config(
{'BLOCK_SIZE_M': 64, 'BLOCK_SIZE_N': 128, 'BLOCK_SIZE_K': 32, 'GROUP_SIZE_M': 8, 'waves_per_eu': 3},
num_warps=4, num_stages=0),
num_warps=4, num_stages=2),
triton.Config(
{'BLOCK_SIZE_M': 64, 'BLOCK_SIZE_N': 64, 'BLOCK_SIZE_K': 32, 'GROUP_SIZE_M': 1, 'waves_per_eu': 8},
num_warps=4, num_stages=0),
num_warps=4, num_stages=2),
]


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2 changes: 1 addition & 1 deletion third_party/amd/backend/compiler.py
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Expand Up @@ -169,7 +169,7 @@ def make_ttgir(mod, metadata, options):
passes.ttgpuir.add_remove_layout_conversions(pm)
amd.passes.ttgpuir.add_optimize_epilogue(pm)
passes.ttgpuir.add_optimize_dot_operands(pm, True)
use_new_pipeliner = os.getenv("TRITON_HIP_USE_NEW_STREAM_PIPELINE", "0") == "1"
use_new_pipeliner = os.getenv("TRITON_HIP_USE_NEW_STREAM_PIPELINE", "1") == "1"
if amd.has_matrix_core_feature(options.arch):
if use_new_pipeliner:
# In the old pipeliner we only support num_stages = 0/1, which means something
Expand Down
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