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asd.txt | ||
asd.png |
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import "stdlib/str.jou" | ||
import "stdlib/ascii.jou" | ||
import "stdlib/io.jou" | ||
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enum LogicOp: | ||
And | ||
Or | ||
Xor | ||
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class LogicGate: | ||
inputs: int*[2] # -1 = undefined, otherwise 0 or 1 | ||
output: int* | ||
op: LogicOp | ||
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def run(self) -> None: | ||
if *self->inputs[0] == -1 or *self->inputs[1] == -1: | ||
return | ||
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i1 = (*self->inputs[0] == 1) | ||
i2 = (*self->inputs[1] == 1) | ||
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if self->op == LogicOp::And: | ||
*self->output = (i1 and i2) as int | ||
elif self->op == LogicOp::Or: | ||
*self->output = (i1 or i2) as int | ||
elif self->op == LogicOp::Xor: | ||
*self->output = (i1 != i2) as int | ||
else: | ||
assert False | ||
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class VariableManager: | ||
variables: int[500] | ||
nvariables: int | ||
varnames: byte[4][500] | ||
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def get_var(self, name: byte*) -> int*: | ||
for i = 0; i < self->nvariables; i++: | ||
if strcmp(name, self->varnames[i]) == 0: | ||
return &self->variables[i] | ||
return NULL | ||
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def get_or_create_var(self, name: byte*) -> int*: | ||
exist = self->get_var(name) | ||
if exist != NULL: | ||
return exist | ||
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assert self->nvariables < 500 | ||
i = self->nvariables++ | ||
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assert strlen(name) == 3 | ||
strcpy(self->varnames[i], name) | ||
self->variables[i] = -1 # uninitialized | ||
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return &self->variables[i] | ||
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def get_result(self) -> long: | ||
# Variables starting with z are named z00, z01, z02, ... | ||
# Loop backwards to get bit order right. | ||
zcount = 0 | ||
for i = 0; i < self->nvariables; i++: | ||
if self->varnames[i][0] == 'z': | ||
zcount++ | ||
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result = 0L | ||
for i = zcount-1; i >= 0; i--: | ||
name: byte[100] | ||
sprintf(name, "z%02d", i) | ||
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v = self->get_var(name) | ||
assert v != NULL | ||
if *v == -1: | ||
return -1 | ||
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result *= 2 | ||
result += *v | ||
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return result | ||
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def main() -> int: | ||
varmgr = VariableManager{} | ||
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gates: LogicGate[500] | ||
ngates = 0 | ||
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f = fopen("sampleinput1.txt", "r") | ||
assert f != NULL | ||
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line: byte[100] | ||
while fgets(line, sizeof(line) as int, f) != NULL: | ||
trim_ascii_whitespace(line) | ||
if line[0] == '\0': | ||
# end of initial values, start of logic gates | ||
break | ||
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# initial value of variable, e.g. "x01: 1" | ||
assert strlen(line) == 6 | ||
assert line[3] == ':' | ||
line[3] = '\0' | ||
*varmgr.get_or_create_var(line) = atoi(&line[5]) | ||
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input1, op, input2, output: byte[4] | ||
while fscanf(f, "%3s %3s %3s -> %3s\n", input1, op, input2, output) == 4: | ||
if strcmp(op, "AND") == 0: | ||
op_enum = LogicOp::And | ||
elif strcmp(op, "OR") == 0: | ||
op_enum = LogicOp::Or | ||
elif strcmp(op, "XOR") == 0: | ||
op_enum = LogicOp::Xor | ||
else: | ||
assert False | ||
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assert ngates < sizeof(gates)/sizeof(gates[0]) | ||
gates[ngates++] = LogicGate{ | ||
inputs = [varmgr.get_or_create_var(input1), varmgr.get_or_create_var(input2)], | ||
output = varmgr.get_or_create_var(output), | ||
op = op_enum, | ||
} | ||
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# Check that no gate has multiple outputs hooked up to its input | ||
for i = 0; i < ngates; i++: | ||
for k = 0; k < 2; k++: | ||
var = gates[i].inputs[k] | ||
count = 0 | ||
for g = &gates[0]; g < &gates[ngates]; g++: | ||
if g->output == var: | ||
count++ | ||
assert count <= 1 | ||
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while varmgr.get_result() == -1: | ||
for g = &gates[0]; g < &gates[ngates]; g++: | ||
g->run() | ||
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printf("%lld\n", varmgr.get_result()) # Output: 2024 | ||
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fclose(f) | ||
return 0 |
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