Rework default testbench

CHANGELOG.md

@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 10.11.2024 | 1.10.6.4 | rework default processor testbench | [#1093](https://github.com/stnolting/neorv32/pull/1093) |
 | 06.11.2024 | 1.10.6.3 | minor rtl edits and cleanups | [#1090](https://github.com/stnolting/neorv32/pull/1090) |
 | 02.11.2024 | 1.10.6.2 | :warning: rework processor boot configuration; add new boot-configuration generics | [#1086](https://github.com/stnolting/neorv32/pull/1086) |
 | 01.11.2024 | 1.10.6.1 | :test_tube: convert VHDL memory images into full-scale VHDL packages | [#1084](https://github.com/stnolting/neorv32/pull/1084) |

docs/datasheet/soc_uart.adoc

@@ -116,7 +116,7 @@ unconnected. If the CTS handshake is not required it has to be tied to zero.
 The UART provides a _simulation-only_ mode to dump console data as well as raw data directly to a file. When the simulation
 mode is enabled (by setting the `UART_CTRL_SIM_MODE` bit) there will be **no** physical transaction on the `uart0_txd_o` signal.
 Instead, all data written to the `DATA` register is immediately dumped to a file. Data written to `DATA[7:0]` will be dumped as
-ASCII chars to a file named `neorv32.uart0.sim_mode.text.out`. Additionally, the ASCII data is printed to the simulator console.
+ASCII chars to a file named `neorv32.uart0_sim_mode.out`. Additionally, the ASCII data is printed to the simulator console.
 
 Both file are created in the simulation's home folder.
 
@@ -192,7 +192,7 @@ as for the primary UART. The RX and TX interrupts of UART1 are mapped to differe
 **Simulation Mode**
 
 The secondary UART (UART1) provides the same simulation options as the primary UART (UART0). However, output data is
-written to UART1-specific file `neorv32.uart1.sim_mode.text.out`. This data is also printed to the simulator console.
+written to UART1-specific file `neorv32.uart1_sim_mode.out`. This data is also printed to the simulator console.
 
 
 **Register Map**

rtl/core/neorv32_package.vhd

@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100603"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100604"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 
@@ -181,6 +181,43 @@ package neorv32_package is
     ack  : std_ulogic;
   end record;
 
+  -- External Bus Interface (XBUS / Wishbone) -----------------------------------------------
+  -- -------------------------------------------------------------------------------------------
+  -- xbus request --
+  type xbus_req_t is record
+    addr : std_ulogic_vector(31 downto 0); -- access address
+    data : std_ulogic_vector(31 downto 0); -- write data
+    tag  : std_ulogic_vector(2 downto 0); -- access tag
+    we   : std_ulogic; -- read/write
+    sel  : std_ulogic_vector(3 downto 0); -- byte enable
+    stb  : std_ulogic; -- strobe
+    cyc  : std_ulogic; -- valid cycle
+  end record;
+
+  -- xbus response --
+  type xbus_rsp_t is record
+    data : std_ulogic_vector(31 downto 0); -- read data, valid if ack=1
+    ack  : std_ulogic; -- access acknowledge
+    err  : std_ulogic; -- access error
+  end record;
+
+  -- endpoint (response) termination --
+  constant xbus_rsp_terminate_c : xbus_rsp_t := (
+    data => (others => '0'),
+    ack  => '0',
+    err  => '0'
+  );
+
+  -- External Stream-Link Interface (SLINK / AXI4-Stream) -----------------------------------
+  -- -------------------------------------------------------------------------------------------
+  type slink_t is record
+    data  : std_ulogic_vector(31 downto 0); -- data
+    addr  : std_ulogic_vector(3 downto 0); -- source/destination ID
+    valid : std_ulogic; -- source valid
+    last  : std_ulogic; -- last element of packet
+    ready : std_ulogic; -- sink ready
+  end record;
+
 -- **********************************************************************************************************
 -- RISC-V ISA Definitions
 -- **********************************************************************************************************

rtl/core/neorv32_top.vhd

@@ -1218,7 +1218,7 @@ begin
       neorv32_uart0_inst: entity neorv32.neorv32_uart
       generic map (
         SIM_MODE_EN  => true,
-        SIM_LOG_FILE => "neorv32.uart0.sim_mode.text.out",
+        SIM_LOG_FILE => "neorv32.uart0_sim_mode.out",
         UART_RX_FIFO => IO_UART0_RX_FIFO,
         UART_TX_FIFO => IO_UART0_TX_FIFO
       )
@@ -1256,7 +1256,7 @@ begin
       neorv32_uart1_inst: entity neorv32.neorv32_uart
       generic map (
         SIM_MODE_EN  => true,
-        SIM_LOG_FILE => "neorv32.uart1.sim_mode.text.out",
+        SIM_LOG_FILE => "neorv32.uart1_sim_mode.out",
         UART_RX_FIFO => IO_UART1_RX_FIFO,
         UART_TX_FIFO => IO_UART1_TX_FIFO
       )

sim/ghdl.run.sh

@@ -4,34 +4,47 @@ set -e
 
 cd $(dirname "$0")
 
-echo "[TIP] Compile application with USER_FLAGS+=-DUART[0/1]_SIM_MODE to enable UART[0/1]'s simulation mode (redirect UART output to simulator console)."
-
-# Prepare simulation output files for UART0 and UART 1
-# - Testbench receiver log file (neorv32.testbench_uart?.out)
-# - Direct simulation output (neorv32.uart?.sim_mode.text.out)
-for uart in 0 1; do
-  for item in \
-    testbench_uart"$uart" \
-    uart"$uart".sim_mode.text; do
-    touch neorv32."$item".out
-    chmod 777 neorv32."$item".out
-  done
-done
-
+NEORV32_RTL=${NEORV32_RTL:-../rtl}
+FILE_LIST=`cat $NEORV32_RTL/file_list_soc.f`
+CORE_SRCS="${FILE_LIST//NEORV32_RTL_PATH_PLACEHOLDER/"$NEORV32_RTL"}"
 GHDL="${GHDL:-ghdl}"
 
+# Prepare UART SIM_MODE output files
+touch neorv32.uart0_sim_mode.out neorv32.uart1_sim_mode.out
+chmod 777 neorv32.uart0_sim_mode.out neorv32.uart1_sim_mode.out
+
+# Prepare testbench UART log files
+touch neorv32_tb.uart0_rx.out neorv32_tb.uart1_rx.out
+chmod 777 neorv32_tb.uart0_rx.out neorv32_tb.uart1_rx.out
+
+# GHDL build directory
+mkdir -p build
+
+# GHDL import
+$GHDL -i --work=neorv32 --workdir=build \
+  $CORE_SRCS \
+  "$NEORV32_RTL"/processor_templates/*.vhd \
+  "$NEORV32_RTL"/system_integration/*.vhd \
+  "$NEORV32_RTL"/test_setups/*.vhd \
+  neorv32_tb.vhd \
+  sim_uart_rx.vhd \
+  xbus_gateway.vhd \
+  xbus_memory.vhd
+
+# GHDL analyze
 $GHDL -m --work=neorv32 --workdir=build neorv32_tb
 
+# GHDL run parameters
 if [ -z "$1" ]
   then
     GHDL_RUN_ARGS="${@:---stop-time=10ms}"
   else
-    # Lets pass down all the parameters to GHDL instead of just 1
+    # Let's pass down all the parameters to GHDL
     GHDL_RUN_ARGS=$@
 fi
+echo "GHDL simulation run parameters: $GHDL_RUN_ARGS";
 
-echo "Using simulation run arguments: $GHDL_RUN_ARGS";
-
+# GHDL run
 runcmd="$GHDL -r --work=neorv32 --workdir=build neorv32_tb \
   --max-stack-alloc=0 \
   --ieee-asserts=disable \

sim/ghdl.sh

@@ -5,8 +5,7 @@ set -e
 
 cd $(dirname "$0")
 
-# Setup simulation
-/bin/bash ghdl.setup.sh
+echo "[TIP] Compile application with USER_FLAGS+=-DUART[0/1]_SIM_MODE to enable UART[0/1]'s simulation mode (redirect UART output to simulator console)."
 
 # Run simulation (pass down more than 1 parameter to GHDL)
 /bin/bash ghdl.run.sh $@