Apply custom Si settings via CMIS: SONiC xcvrd platform common changes

sonic_platform_base/sonic_xcvr/api/public/cmis.py

@@ -2097,6 +2097,117 @@ def set_application(self, channel, appl_code):
         # Apply DataPathInit
         return self.xcvr_eeprom.write("%s_%d" % (consts.STAGED_CTRL_APPLY_DPINIT_FIELD, 0), channel)
 
+    def set_module_si_settings(self, host_lanes_mask, appl_code, optics_si_dict):
+        # Read and cache the existing SCS0 TX CTRL data
+        si_settings = self.xcvr_eeprom.read(consts.STAGED_CTRL0_TX_CTRL_FIELD)
+        if si_settings is None:
+            return None
+
+        # Replace the new values with cached SI values
+        for si_keys in optics_si_dict:
+            if si_keys in si_settings:
+                si_settings[si_keys] = optics_si_dict[si_keys]
+
+        # Read and cache all the SI CTRL Advertisement
+        bit_0 = 0b00000001
+        bit_1 = 0b00000010
+        bit_2 = 0b00000100
+        bit_3 = 0b00001000
+        bit_4 = 0b00010000
+        bit_5 = 0b00100000
+        bit_6 = 0b01000000
+        bit_7 = 0b10000000
+
+        # Module TX/RX Characteristic Advertisement Support Values
+        tx_input_eq_max_val = self.xcvr_eeprom.read(consts.TX_INPUT_EQ_MAX)
+        rx_output_amp_supported_val = self.xcvr_eeprom.read(consts.RX_OUTPUT_LEVEL_SUPPORT)
+        rx_output_eq_pre_max_val = self.xcvr_eeprom.read(consts.RX_OUTPUT_EQ_PRE_CURSOR_MAX)
+        rx_output_eq_post_max_val = self.xcvr_eeprom.read(consts.RX_OUTPUT_EQ_POST_CURSOR_MAX)
+
+        # TX/RX Control Advertisement Support
+        tx_si_ctrl_advt = self.xcvr_eeprom.read(consts.TX_SI_CTRL_ADVT)
+        rx_si_ctrl_advt = self.xcvr_eeprom.read(consts.RX_SI_CTRL_ADVT)
+
+        tx_cdr_supported = tx_si_ctrl_advt & bit_0
+        tx_input_eq_fixed_supported = (tx_si_ctrl_advt & bit_2) >> 2
+        tx_input_adaptive_eq_supported = (tx_si_ctrl_advt & bit_3) >> 3
+        tx_input_recall_buf1_supported = (tx_si_ctrl_advt & bit_5) >> 5
+        tx_input_recall_buf2_supported = (tx_si_ctrl_advt & bit_6) >> 6
+
+        rx_cdr_supported = rx_si_ctrl_advt & bit_0
+        rx_ouput_amp_ctrl_supported = (rx_si_ctrl_advt & bit_2) >> 2
+        rx_output_eq_pre_ctrl_supported = (rx_si_ctrl_advt & bit_3) >> 3
+        rx_output_eq_post_ctrl_supported = (rx_si_ctrl_advt & bit_4) >> 4
+
+        # Apply the SI settings if supported
+        for si_keys in si_settings:
+            if ((si_keys == consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX and rx_output_eq_pre_ctrl_supported) or
+                (si_keys == consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX and rx_output_eq_post_ctrl_supported) or
+                (si_keys == consts.OUTPUT_AMPLITUDE_TARGET_RX and rx_ouput_amp_ctrl_supported) or
+                (si_keys == consts.FIXED_INPUT_EQ_TARGET_TX and tx_input_eq_fixed_supported)):
+                for lane in range(self.NUM_CHANNELS):
+                    if ((1 << lane) & host_lanes_mask) == 0:
+                        continue
+                    lane = lane+1
+                    si_key_lane = "{}{}".format(si_keys, lane)
+                    val = si_settings[si_keys][si_key_lane]
+                    if ((si_keys == consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX and val <= rx_output_eq_pre_max_val) or
+                        (si_keys == consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX and val <= rx_output_eq_post_max_val) or
+                        (si_keys == consts.OUTPUT_AMPLITUDE_TARGET_RX and val <= rx_output_amp_supported_val) or
+                        (si_keys == consts.FIXED_INPUT_EQ_TARGET_TX and val <= tx_input_eq_max_val)) :
+                        if (lane%2) == 0:
+                            pre_si_key_lane = "{}{}".format(si_keys, lane-1)
+                            pre_val = self.xcvr_eeprom.read(pre_si_key_lane)
+                            val = (val << 4) | pre_val
+                        self.xcvr_eeprom.write(si_key_lane, val)
+            elif (si_keys == consts.ADAPTIVE_INPUT_EQ_RECALLED_TX and 
+                 (tx_input_recall_buf1_supported or tx_input_recall_buf2_supported)):
+                val = 0
+                for lane in range(self.NUM_CHANNELS):
+                    if ((1 << lane) & host_lanes_mask) == 0:
+                        continue
+                    si_key_lane = "{}{}".format(si_keys, lane+1)
+                    si_val = si_settings[si_keys][si_key_lane]
+                    lane %= (self.NUM_CHANNELS//2)
+                    mask = ~(val << (lane*2))
+                    l_data = si_val << (lane*2)
+                    val = (val & mask) | l_data
+                    self.xcvr_eeprom.write(si_key_lane, val)
+            elif ((si_keys == consts.ADAPTIVE_INPUT_EQ_ENABLE_TX and tx_input_adaptive_eq_supported) or
+                  (si_keys == consts.CDR_ENABLE_TX and tx_cdr_supported) or
+                  (si_keys == consts.CDR_ENABLE_RX and rx_cdr_supported)) :
+                val = 0
+                # Read 1 byte data
+                for lane in range(self.NUM_CHANNELS):
+                    si_key_lane = "{}{}".format(si_keys, lane+1)
+                    data  = self.xcvr_eeprom.read(si_key_lane)
+                    val |= (data << lane)
+                # Write only applicable field
+                for lane in range(self.NUM_CHANNELS):
+                    if ((1 << lane) & host_lanes_mask) == 0:
+                        continue
+                    si_key_lane = "{}{}".format(si_keys, lane+1)
+                    si_val = si_settings[si_keys][si_key_lane]
+                    val &= ~(1 << lane)
+                    val |= (si_val << lane)
+                    self.xcvr_eeprom.write(si_key_lane, val)
+
+        # Apply ApSel with EC = 1
+        lane_first = -1
+        for lane in range(self.NUM_CHANNELS):
+            if ((1 << lane) & host_lanes_mask) == 0:
+                continue
+            if lane_first < 0:
+                lane_first = lane
+            addr = "{}_{}_{}".format(consts.STAGED_CTRL_APSEL_FIELD, 0, lane + 1)
+            data = (appl_code << 4) | (lane_first << 1)
+            # set EC = 1
+            data |= 0x1
+            self.xcvr_eeprom.write(addr, data)
+
+        # Apply DataPathInit
+        return self.xcvr_eeprom.write("%s_%d" % (consts.STAGED_CTRL_APPLY_DPINIT_FIELD, 0), host_lanes_mask)
+
     def get_error_description(self):
         dp_state = self.get_datapath_state()
         conf_state = self.get_config_datapath_hostlane_status()

sonic_platform_base/sonic_xcvr/fields/consts.py

@@ -299,6 +299,41 @@
 STAGED_CTRL_APPLY_IMMEDIATE_FIELD = "Staged Control Set Apply Immediate"
 STAGED_CTRL_APSEL_FIELD = "Staged Control Set ApSel"
 
+STAGED_CTRL0_TX_CTRL_FIELD = "Staged Control TX Control"
+
+TX_INPUT_EQ_MAX = "TXInputEqMax"
+RX_OUTPUT_LEVEL_SUPPORT = "RX Output Level Supported"
+RX_OUTPUT_LEVEL_0_SUPPORTED = "RXOutputLevel0Supported"
+RX_OUTPUT_LEVEL_1_SUPPORTED = "RXOutputLevel1Supported"
+RX_OUTPUT_LEVEL_2_SUPPORTED = "RXOutputLevel2Supported"
+RX_OUTPUT_LEVEL_3_SUPPORTED = "RXOutputLevel3Supported"
+RX_OUTPUT_EQ_PRE_CURSOR_MAX = "RXOutputEqPreCursorMax"
+RX_OUTPUT_EQ_POST_CURSOR_MAX = "RXOutputEqPostCursorMax"
+
+SIGNAL_INTEGRITY_CTRL_ADVT_FIELD = "Signal Integrity Control Advertisement"
+TX_SI_CTRL_ADVT = "TX SI Control Advertisement"
+TX_CDR_SUPPORT_FIELD = "TXCDRSupported"
+TX_CDR_BYPASS_CTRL_FIELD = "TXCDRBypassSupported"
+TX_INPUT_EQ_FIXED_MANUAL_CTRL_SUPPORT_FIELD = "TXInputEqFixedManualSupported"
+TX_INPUT_ADAPTIVE_EQ_SUPPORT_FIELD = "TXInputAdaptiveEqSupported"
+TX_INPUT_EQ_FREEZE_SUPPORT_FIELD = "TXInputEqFreezeSupported"
+TX_INPUT_EQ_RECALL_BUF_SUPPORT_FIELD = "TXInputEqRecallBufSupported"
+RX_SI_CTRL_ADVT = "RX SI Control Advertisement"
+RX_CDR_SUPPORT_FIELD = "RxCDRSupported"
+RX_CDR_BYPASS_CTRL_FIELD = "RXCDRBypassSupported"
+RX_OUTPUT_AMP_CTRL_SUPPORT_FIELD = "RXOutputAmpSupported"
+RX_OUTPUT_EQ_CTRL_SUPPORT_FIELD = "RXOutputEQSupported"
+
+ACTIVE_CTRL_FIELD = "Active Control Set"
+ADAPTIVE_INPUT_EQ_ENABLE_TX = "AdaptiveInputEqEnableTx"
+ADAPTIVE_INPUT_EQ_RECALLED_TX = "AdaptiveInputEqRecalledTx"
+FIXED_INPUT_EQ_TARGET_TX = "FixedInputEqTargetTx"
+CDR_ENABLE_TX = "CDREnableTx"
+CDR_ENABLE_RX = "CDREnableRx"
+OUTPUT_EQ_PRE_CURSOR_TARGET_RX = "OutputEqPreCursorTargetRx"
+OUTPUT_EQ_POST_CURSOR_TARGET_RX = "OutputEqPostCursorTargetRx"
+OUTPUT_AMPLITUDE_TARGET_RX = "OutputAmplitudeTargetRx"
+
 # C-CMIS
 
 # Module configuration support fields

sonic_platform_base/sonic_xcvr/mem_maps/public/cmis.py

@@ -195,6 +195,21 @@ def __init__(self, codes):
             NumberRegField(consts.PAGE_SUPPORT_ADVT_FIELD, self.getaddr(0x1, 142),
                 RegBitField(consts.VDM_SUPPORTED, 6),
             ),
+            NumberRegField(consts.TX_INPUT_EQ_MAX, self.getaddr(0x1, 153),
+                *(RegBitField("Bit%d" % (bit), bit) for bit in range (0 , 4))
+            ),
+            NumberRegField(consts.RX_OUTPUT_LEVEL_SUPPORT, self.getaddr(0x1, 153),
+                RegBitField(consts.RX_OUTPUT_LEVEL_0_SUPPORTED, 4),
+                RegBitField(consts.RX_OUTPUT_LEVEL_1_SUPPORTED, 5),
+                RegBitField(consts.RX_OUTPUT_LEVEL_2_SUPPORTED, 6),
+                RegBitField(consts.RX_OUTPUT_LEVEL_3_SUPPORTED, 7),
+            ),
+            NumberRegField(consts.RX_OUTPUT_EQ_PRE_CURSOR_MAX, self.getaddr(0x1, 154),
+                *(RegBitField("Bit%d" % (bit), bit) for bit in range (0 , 4))
+            ),
+            NumberRegField(consts.RX_OUTPUT_EQ_POST_CURSOR_MAX, self.getaddr(0x1, 154),
+                *(RegBitField("Bit%d" % (bit), bit) for bit in range (4 , 8))
+            ),
             NumberRegField(consts.CTRLS_ADVT_FIELD, self.getaddr(0x1, 155),
                 RegBitField(consts.TX_DISABLE_SUPPORT_FIELD, 1),
                 size=2, format="<H"
@@ -461,6 +476,80 @@ def __init__(self, codes):
                 for lane in range(1, 9))
         )
 
+        self.SIGNAL_INTEGRITY_CTRL_ADVT = RegGroupField(consts.SIGNAL_INTEGRITY_CTRL_ADVT_FIELD,
+            NumberRegField(consts.TX_SI_CTRL_ADVT, self.getaddr(0x1, 161),
+                RegBitField(consts.TX_CDR_SUPPORT_FIELD, 0),
+                RegBitField(consts.TX_CDR_BYPASS_CTRL_FIELD, 1),
+                RegBitField(consts.TX_INPUT_EQ_FIXED_MANUAL_CTRL_SUPPORT_FIELD, 2),
+                RegBitField(consts.TX_INPUT_ADAPTIVE_EQ_SUPPORT_FIELD, 3),
+                RegBitField(consts.TX_INPUT_EQ_FREEZE_SUPPORT_FIELD, 4),
+                RegBitField(consts.TX_INPUT_EQ_RECALL_BUF_SUPPORT_FIELD, 5),
+                RegBitField(consts.TX_INPUT_EQ_RECALL_BUF_SUPPORT_FIELD, 6),
+            ),
+            NumberRegField(consts.TX_INPUT_EQ_RECALL_BUF_SUPPORT_FIELD, self.getaddr(0x1, 161),
+                *(RegBitField("Bit%d" % (bit), bit) for bit in range (5 , 7))
+            ),
+
+            NumberRegField(consts.RX_SI_CTRL_ADVT, self.getaddr(0x1, 162),
+                RegBitField(consts.RX_CDR_SUPPORT_FIELD, 0),
+                RegBitField(consts.RX_CDR_BYPASS_CTRL_FIELD, 1),
+                RegBitField(consts.RX_OUTPUT_AMP_CTRL_SUPPORT_FIELD, 2),
+                RegBitField(consts.RX_OUTPUT_EQ_CTRL_SUPPORT_FIELD, 3),
+                RegBitField(consts.RX_OUTPUT_EQ_CTRL_SUPPORT_FIELD, 4),
+            ),
+            NumberRegField(consts.RX_OUTPUT_EQ_CTRL_SUPPORT_FIELD, self.getaddr(0x1, 162),
+                *(RegBitField("Bit%d" % (bit), bit) for bit in range (3 , 5))
+            ),
+
+        )
+
+        self.STAGED_CTRL0_TX_CTRL = RegGroupField(consts.STAGED_CTRL0_TX_CTRL_FIELD,
+            RegGroupField(consts.ADAPTIVE_INPUT_EQ_ENABLE_TX,
+                *(NumberRegField("%s%d" % (consts.ADAPTIVE_INPUT_EQ_ENABLE_TX, lane) , self.getaddr(0x10, 153),
+                    RegBitField("Bit%d" % (lane-1), (lane-1)), ro=False
+                  )
+                  for lane in range(1, 9))
+            ),
+            RegGroupField(consts.ADAPTIVE_INPUT_EQ_RECALLED_TX,
+                *(NumberRegField("%s%d" % (consts.ADAPTIVE_INPUT_EQ_RECALLED_TX, lane) , self.getaddr(0x10, 154 + int((lane-1)/4)), ro=False,
+                    *(RegBitField("Bit%d" % bit, bit) for bit in [range(6, 8), range(4, 6), range(2, 4), range(0, 2)][lane%4]))
+                 for lane in range(1, 9))
+            ),
+            RegGroupField(consts.FIXED_INPUT_EQ_TARGET_TX,
+                *(NumberRegField("%s%d" % (consts.FIXED_INPUT_EQ_TARGET_TX, lane) , self.getaddr(0x10, 156 + int((lane-1)/2)), ro=False,
+                    *(RegBitField("Bit%d" % bit, bit) for bit in [range(4, 8), range(0, 4)][lane%2]))
+                for lane in range(1, 9))
+            ),
+            RegGroupField(consts.CDR_ENABLE_TX,
+                *(NumberRegField("%s%d" % (consts.CDR_ENABLE_TX, lane), self.getaddr(0x10, 160),
+                    RegBitField("Bit%d" % (lane-1), (lane-1)), ro=False
+                 )
+                 for lane in range(1, 9))
+            ),
+            RegGroupField(consts.CDR_ENABLE_RX,
+                *(NumberRegField("%s%d" % (consts.CDR_ENABLE_RX, lane), self.getaddr(0x10, 161),
+                    RegBitField("Bit%d" % (lane-1), (lane-1)), ro=False
+                 )
+                 for lane in range(1, 9))
+            ),
+            RegGroupField(consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX,
+                *(NumberRegField("%s%d" % (consts.OUTPUT_EQ_PRE_CURSOR_TARGET_RX, lane) , self.getaddr(0x10, 162 + int((lane-1)/2)), ro=False,
+                    *(RegBitField("Bit%d" % bit, bit) for bit in [range(4, 8), range(0, 4)][lane%2]))
+                for lane in range(1, 9))
+            ),
+            RegGroupField(consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX,
+                *(NumberRegField("%s%d" % (consts.OUTPUT_EQ_POST_CURSOR_TARGET_RX, lane) , self.getaddr(0x10, 166 + int((lane-1)/2)), ro=False,
+                    *(RegBitField("Bit%d" % bit, bit) for bit in [range(4, 8), range(0, 4)][lane%2]))
+                for lane in range(1, 9))
+            ),
+
+            RegGroupField(consts.OUTPUT_AMPLITUDE_TARGET_RX,
+                *(NumberRegField("%s%d" % (consts.OUTPUT_AMPLITUDE_TARGET_RX, lane) , self.getaddr(0x10, 170 + int((lane-1)/2)), ro=False,
+                    *(RegBitField("Bit%d" % bit, bit) for bit in [range(4, 8), range(0, 4)][lane%2]))
+                for lane in range(1, 9))
+            ),
+        )
+
         # TODO: add remaining fields
 
     def getaddr(self, page, offset, page_size=128):

tests/sonic_xcvr/test_cmis.py

@@ -2215,6 +2215,55 @@ def test_set_application(self):
         self.api.set_application(0x7fffffff, 1)
         assert self.api.xcvr_eeprom.write.call_count == self.api.NUM_CHANNELS + 1
 
+    def test_set_module_si_eq_pre_settings(self):
+        optics_si_eq_pre_dict =  { "OutputEqPreCursorTargetRx":{
+                                     "OutputEqPreCursorTargetRx1":3, "OutputEqPreCursorTargetRx2":3, "OutputEqPreCursorTargetRx3":3, "OutputEqPreCursorTargetRx4":3,
+                                     "OutputEqPreCursorTargetRx5":3, "OutputEqPreCursorTargetRx6":3, "OutputEqPreCursorTargetRx7":3, "OutputEqPreCursorTargetRx8":3 }
+                                 }
+        optics_si_dict = { "OutputEqPreCursorTargetRx":{
+                             "OutputEqPreCursorTargetRx1":2, "OutputEqPreCursorTargetRx2":2, "OutputEqPreCursorTargetRx3":2, "OutputEqPreCursorTargetRx4":2,
+                             "OutputEqPreCursorTargetRx5":2, "OutputEqPreCursorTargetRx6":2, "OutputEqPreCursorTargetRx7":2, "OutputEqPreCursorTargetRx8":2 }
+                         }
+        self.api.xcvr_eeprom.read = MagicMock()
+        self.api.xcvr_eeprom.write = MagicMock()
+        mock_resp = [optics_si_eq_pre_dict, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff]
+        self.api.xcvr_eeprom.read.side_effect = mock_resp
+        self.api.set_module_si_settings(0x01 , 1, optics_si_dict)
+        assert self.api.xcvr_eeprom.write.call_count == 1 + 1 + 1
+
+    def test_set_module_si_eq_en_settings(self):
+        optics_si_eq_en_dict =  { "AdaptiveInputEqEnableTx":{
+                                    "AdaptiveInputEqEnableTx1":0, "AdaptiveInputEqEnableTx2":0, "AdaptiveInputEqEnableTx3":0, "AdaptiveInputEqEnableTx4":0,
+                                    "AdaptiveInputEqEnableTx5":0, "AdaptiveInputEqEnableTx6":0, "AdaptiveInputEqEnableTx7":0, "AdaptiveInputEqEnableTx8":0 }
+                                }
+        optics_si_dict = { "AdaptiveInputEqEnableTx":{
+                             "AdaptiveInputEqEnableTx1":1, "AdaptiveInputEqEnableTx2":1, "AdaptiveInputEqEnableTx3":1, "AdaptiveInputEqEnableTx4":1,
+                             "AdaptiveInputEqEnableTx5":1, "AdaptiveInputEqEnableTx6":1, "AdaptiveInputEqEnableTx7":1, "AdaptiveInputEqEnableTx8":1 }
+                         }
+        self.api.xcvr_eeprom.read = MagicMock()
+        self.api.xcvr_eeprom.write = MagicMock()
+        mock_resp = [optics_si_eq_en_dict, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff]
+        self.api.xcvr_eeprom.read.side_effect = mock_resp
+        self.api.set_module_si_settings(0xff , 1, optics_si_dict)
+        assert self.api.xcvr_eeprom.write.call_count == 8 + 8 + 1
+
+    def test_set_module_si_eq_recall_settings(self):
+        optics_si_eq_recall_dict = { "AdaptiveInputEqRecalledTx":{
+                                       "AdaptiveInputEqRecalledTx1":0, "AdaptiveInputEqRecalledTx2":0, "AdaptiveInputEqRecalledTx3":0, "AdaptiveInputEqRecalledTx4":0,
+                                       "AdaptiveInputEqRecalledTx5":0, "AdaptiveInputEqRecalledTx6":0, "AdaptiveInputEqRecalledTx7":0, "AdaptiveInputEqRecalledTx8":0 }
+                                   }
+        optics_si_dict = { "AdaptiveInputEqRecalledTx":{
+                             "AdaptiveInputEqRecalledTx1":1, "AdaptiveInputEqRecalledTx2":1, "AdaptiveInputEqRecalledTx3":1, "AdaptiveInputEqRecalledTx4":1,
+                             "AdaptiveInputEqRecalledTx5":1, "AdaptiveInputEqRecalledTx6":1, "AdaptiveInputEqRecalledTx7":1, "AdaptiveInputEqRecalledTx8":1 }
+                         }
+        self.api.xcvr_eeprom.read = MagicMock()
+        self.api.xcvr_eeprom.write = MagicMock()
+        mock_resp = [optics_si_eq_recall_dict, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff]
+        self.api.xcvr_eeprom.read.side_effect = mock_resp
+        self.api.set_module_si_settings(0x0f , 1, optics_si_dict)
+        assert self.api.xcvr_eeprom.write.call_count == 4 + 4 + 1
+
     def test_get_error_description(self):
         self.api.get_module_state = MagicMock()
         self.api.get_module_state.return_value = 'ModuleReady'