Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Allow writing CBO bits in xenvcfg #635

Merged
merged 1 commit into from
Jan 6, 2025
Merged

Allow writing CBO bits in xenvcfg #635

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
13 changes: 10 additions & 3 deletions model/riscv_sys_regs.sail
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -349,6 +349,9 @@ function legalize_menvcfg(o : MEnvcfg, v : bits(64)) -> MEnvcfg = {
let v = Mk_MEnvcfg(v);
[o with
FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0,
CBZE = if extensionEnabled(Ext_Zicboz) then v[CBZE] else 0b0,
CBCFE = if extensionEnabled(Ext_Zicbom) then v[CBCFE] else 0b0,
CBIE = if extensionEnabled(Ext_Zicbom) then (if v[CBIE] != 0b10 then v[CBIE] else 0b00) else 0b00,
jordancarlin marked this conversation as resolved.
Show resolved Hide resolved
STCE = if extensionEnabled(Ext_Sstc) then v[STCE] else 0b0,
// Other extensions are not implemented yet so all other fields are read only zero.
]
Expand All @@ -358,12 +361,16 @@ function legalize_senvcfg(o : SEnvcfg, v : xlenbits) -> SEnvcfg = {
let v = Mk_SEnvcfg(v);
[o with
FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0,
CBZE = if extensionEnabled(Ext_Zicboz) then v[CBZE] else 0b0,
CBCFE = if extensionEnabled(Ext_Zicbom) then v[CBCFE] else 0b0,
CBIE = if extensionEnabled(Ext_Zicbom) then (if v[CBIE] != 0b10 then v[CBIE] else 0b00) else 0b00,
// Other extensions are not implemented yet so all other fields are read only zero.
];
]
}

register menvcfg : MEnvcfg
register senvcfg : SEnvcfg
// Initialised to legal values in case some bits are hard-coded to 1.
register menvcfg : MEnvcfg = legalize_menvcfg(Mk_MEnvcfg(zeros()), zeros())
register senvcfg : SEnvcfg = legalize_senvcfg(Mk_SEnvcfg(zeros()), zeros())

mapping clause csr_name_map = 0x30A <-> "menvcfg"
mapping clause csr_name_map = 0x31A <-> "menvcfgh"
Expand Down
Loading