Merge branch 'main' into smstateen

Signed-off-by: Bill Traynor <[email protected]>

.github/workflows/merge-and-release.yml

@@ -0,0 +1,87 @@
+name: Release New ISA When Merging a PR
+
+on:
+  pull_request:
+    branches:
+      - main
+    types:
+      - closed
+
+jobs:
+  if_merged:
+    if: github.event.pull_request.merged == true
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v4
+
+    - run: |
+        echo The PR was successfully merged.
+
+    - name: Set short SHA
+      run: echo "SHORT_SHA=$(echo ${GITHUB_SHA::7})" >> $GITHUB_ENV
+
+    - name: Get current date
+      run: echo "CURRENT_DATE=$(date +'%Y-%m-%d')" >> $GITHUB_ENV
+
+    - name: Pull Container
+      id: pull_container_image
+      run: |
+          docker pull riscvintl/riscv-docs-base-container-image:latest
+
+    - name: Build Files
+      id: build_files
+      if: steps.pull_container_image.outcome == 'success'
+      run: |
+          docker run --rm -v ${{ github.workspace }}:/build riscvintl/riscv-docs-base-container-image:latest \
+          /bin/sh -c 'cd ./build && make'
+
+    # Upload the priv-isa-asciidoc PDF file
+    - name: Upload priv-isa-asciidoc.pdf
+      if: steps.build_files.outcome == 'success'
+      uses: actions/upload-artifact@v4
+      with:
+        name: priv-isa-asciidoc-${{ env.SHORT_SHA }}.pdf
+        path: ${{ github.workspace }}/build/priv-isa-asciidoc.pdf
+
+    # Upload the priv-isa-asciidoc HTML file
+    - name: Upload priv-isa-asciidoc.html
+      if: steps.build_files.outcome == 'success'
+      uses: actions/upload-artifact@v4
+      with:
+        name: priv-isa-asciidoc-${{ env.SHORT_SHA }}.html
+        path: ${{ github.workspace }}/build/priv-isa-asciidoc.html
+
+    # Upload the unpriv-isa-asciidoc PDF file
+    - name: Upload unpriv-isa-asciidoc.pdf
+      if: steps.build_files.outcome == 'success'
+      uses: actions/upload-artifact@v4
+      with:
+        name: unpriv-isa-asciidoc-${{ env.SHORT_SHA }}.pdf
+        path: ${{ github.workspace }}/build/unpriv-isa-asciidoc.pdf
+
+    # Upload the unpriv-isa-asciidoc HTML file
+    - name: Upload unpriv-isa-asciidoc.html
+      if: steps.build_files.outcome == 'success'
+      uses: actions/upload-artifact@v4
+      with:
+        name: unpriv-isa-asciidoc-${{ env.SHORT_SHA }}.html
+        path: ${{ github.workspace }}/build/unpriv-isa-asciidoc.html
+
+    - name: Create Release
+      uses: softprops/action-gh-release@v1
+      env:
+        GITHUB_TOKEN: ${{ secrets.GHTOKEN }}
+      with:
+        tag_name: riscv-isa-release-${{ env.SHORT_SHA }}-${{ env.CURRENT_DATE }}
+        release_name: Release riscv-isa-release-${{ env.SHORT_SHA }}-${{ env.CURRENT_DATE }}
+        draft: false
+        prerelease: false
+        generate_release_notes: true
+        body: |
+              This release was created by: ${{ github.event.sender.login }}
+              Release of RISC-V ISA, built from commit ${{ env.SHORT_SHA }}, is now available.
+        files: |
+          ${{ github.workspace }}/build/priv-isa-asciidoc.pdf
+          ${{ github.workspace }}/build/priv-isa-asciidoc.html
+          ${{ github.workspace }}/build/unpriv-isa-asciidoc.pdf
+          ${{ github.workspace }}/build/unpriv-isa-asciidoc.html

.gitignore

@@ -1,2 +1,5 @@
 .DS_Store
 .*.swp
+.vscode
+src/.asciidoctor
+src/diag*

dependencies/Gemfile

@@ -2,6 +2,7 @@ source 'https://rubygems.org'
 gem 'asciidoctor'
 gem 'asciidoctor-bibtex'
 gem 'asciidoctor-diagram'
+gem 'mathematical'
 gem 'asciidoctor-mathematical'
 gem 'asciidoctor-pdf'
 gem 'citeproc-ruby'

marchid.md

@@ -60,3 +60,5 @@ RV6           | Nikola Lukić                    | [Nikola Lukić](mailto:lukicn
 ApogeoRV      | Gabriele Tripi                  | [Gabriele Tripi](mailto:[email protected])       | 40               | https://github.com/GabbedT/ApogeoRV
 MicroRV32      | AGRA, Group of Computer Architecture, University of Bremen | [RISC-V @ AGRA](mailto:[email protected])       | 41               | https://github.com/agra-uni-bremen/microrv32
 QEMU          | qemu.org                        | [QEMU Mailing List](mailto:[email protected])           | 42               | https://qemu.org
+KianV         | Hirosh Dabui                    | [Hirosh Dabui](mailto:[email protected])                      | 43               | https://github.com/splinedrive/kianRiscV
+Coreblocks    | Kuźnia Rdzeni, University of Wrocław | [Coreblocks Team](mailto:[email protected])    | 44               | https://github.com/kuznia-rdzeni/coreblocks

src/a-st-ext.adoc

@@ -62,10 +62,11 @@ if the reservation is still valid and the reservation set contains the
 bytes being written. If the SC.W succeeds, the instruction writes the
 word in _rs2_ to memory, and it writes zero to _rd_. If the SC.W fails,
 the instruction does not write to memory, and it writes a nonzero value
-to _rd_. Regardless of success or failure, executing an SC.W instruction
-invalidates any reservation held by this hart. LR.D and SC.D act
-analogously on doublewords and are only available on RV64. For RV64,
-LR.W and SC.W sign-extend the value placed in _rd_.
+to _rd_.  For the purposes of memory protection, a failed SC.W may be
+treated like a store.  Regardless of success or failure, executing an
+SC.W instruction invalidates any reservation held by this hart. LR.D and
+SC.D act analogously on doublewords and are only available on RV64. For
+RV64, LR.W and SC.W sign-extend the value placed in _rd_.
 
 [NOTE]
 ====

src/c-st-ext.adoc

@@ -298,7 +298,7 @@ registers.
 ==== Stack-Pointer-Based Loads and Stores
 
 include::images/wavedrom/c-sp-load-store.adoc[]
-[c-sp-load-store]
+[[c-sp-load-store]]
 //.Stack-Pointer-Based Loads and Stores--these instructions use the CI format.
 
 These instructions use the CI format.
@@ -336,7 +336,7 @@ _zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It
 expands to `fld rd, offset(x2)`.
 
 include::images/wavedrom/c-sp-load-store-css.adoc[]
-[c-sp-load-store-css]
+[[c-sp-load-store-css]]
 //.Stack-Pointer-Based Loads and Stores--these instructions use the CSS format.
 
 These instructions use the CSS format.