Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

target/riscv: early exit support for memory access operations #1134

Open
wants to merge 1 commit into
base: riscv
Choose a base branch
from

Conversation

fk-sc
Copy link
Contributor

@fk-sc fk-sc commented Sep 20, 2024

(1) Error code and skip_reason string were replaced with memory access
status. It allows to specify whether OpenOCD should exit the access
early.
(2) Slightly refactored read_memory and 'write_memory' functions.

@fk-sc
Copy link
Contributor Author

fk-sc commented Sep 20, 2024

@MarekVCodasip, @JanMatCodasip, please take a look

en-sc
en-sc previously approved these changes Sep 20, 2024
Copy link
Collaborator

@en-sc en-sc left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM (reviewed internally).

(1) Error code and 'skip_reason' string were replaced with memory access
    status. It allows to specify whether OpenOCD should exit the access
    early.
(2) Slightly refactored 'read_memory' and 'write_memory' functions.

Checkpatch-ignore: MACRO_ARG_PRECEDENCE, MULTISTATEMENT_MACRO_USE_DO_WHILE
Checkpatch-ignore: TRAILING_SEMICOLON
Signed-off-by: Farid Khaydari <[email protected]>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants