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@mp-17
mp-17 committed May 17, 2024
1 parent 236cabd commit 40df5d2
Showing 1 changed file with 34 additions and 29 deletions.
63 changes: 34 additions & 29 deletions hw/ip/spatz/src/spatz_vlsu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -140,10 +140,11 @@ module spatz_vlsu
id_t [NrInterfaces-1:0] [N_FU-1:0] store_count_q;
id_t [NrInterfaces-1:0] [N_FU-1:0] store_count_d;

for (int intf = 0; intf < NrInterfaces; intf++) begin : gen_store_cnt_intf
for (int fu = 0; fu < N_FU; fu++) begin : gen_store_cnt_intf_fu
for (genvar intf = 0; intf < NrInterfaces; intf++) begin : gen_store_count_q_intf
for (genvar fu = 0; fu < N_FU; fu++) begin : gen_store_count_q_intf_fu
`FF(store_count_q[intf][fu], store_count_d[intf][fu], '0)
end: gen_store_count_q
end: gen_store_count_q_intf_fu
end: gen_store_count_q_intf

always_comb begin: proc_store_count
// Maintain state
Expand All @@ -153,7 +154,7 @@ module spatz_vlsu
for (int fu = 0; fu < N_FU; fu++) begin
automatic int unsigned port = intf * N_FU + fu;

if (spatz_mem_req_o[intf][fu].write && spatz_mem_req_valid_o[intf][fu] && spatz_mem_req_ready_i[intf][fu])
if (spatz_mem_req_o[port].write && spatz_mem_req_valid_o[port] && spatz_mem_req_ready_i[port])
// Did we send a store?
store_count_d[intf][fu]++;

Expand Down Expand Up @@ -430,8 +431,8 @@ module spatz_vlsu
vrf_addr_t [NrInterfaces-1:0] vs2_vreg_addr;

// Current element index and byte index that are being accessed at the register file
vreg_elem_t vd_elem_id;
vreg_elem_t vs2_elem_id_d, vs2_elem_id_q;
vreg_elem_t [NrInterfaces-1:0] vd_elem_id;
vreg_elem_t [NrInterfaces-1:0] vs2_elem_id_d, vs2_elem_id_q;
`FF(vs2_elem_id_q, vs2_elem_id_d, '0)

// Pending indexes
Expand All @@ -441,7 +442,7 @@ module spatz_vlsu
addr_offset_t [NrInterfaces-1:0] [N_FU-1:0] mem_req_addr_offset;
for (genvar intf = 0; intf < NrInterfaces; intf++) begin: gen_mem_req_addr_intf
for (genvar fu = 0; fu < N_FU; fu++) begin: gen_mem_req_addr_intf_fu
automatic int unsigned port = intf * N_FU + fu;
localparam int unsigned port = intf * N_FU + fu;

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[verible-verilog-lint] hw/ip/spatz/src/spatz_vlsu.sv#L445 

Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]
Raw output 
message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]" location:{path:"hw/ip/spatz/src/spatz_vlsu.sv" range:{start:{line:445 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

logic [31:0] addr;
logic [31:0] stride;
Expand All @@ -464,9 +465,9 @@ module spatz_vlsu

// Index
unique case (mem_spatz_req.op_mem.ew)
EW_8 : offset = $signed(vrf_rdata_i[1][8 * word_index +: 8]);
EW_16: offset = $signed(vrf_rdata_i[1][8 * word_index +: 16]);
default: offset = $signed(vrf_rdata_i[1][8 * word_index +: 32]);
EW_8 : offset = $signed(vrf_rdata_i[intf][1][8 * word_index +: 8]);
EW_16: offset = $signed(vrf_rdata_i[intf][1][8 * word_index +: 16]);
default: offset = $signed(vrf_rdata_i[intf][1][8 * word_index +: 32]);
endcase
end else begin
offset = ({mem_counter_q[intf][fu][$bits(vlen_t)-1:MAXEW] << $clog2(NrMemPorts), mem_counter_q[intf][fu][int'(MAXEW)-1:0]} + (port << MAXEW)) * stride;
Expand All @@ -476,16 +477,16 @@ module spatz_vlsu
mem_req_addr[intf][fu] = (addr >> MAXEW) << MAXEW;
mem_req_addr_offset[intf][fu] = addr[int'(MAXEW)-1:0];

pending_index[intf][fu] = (mem_idx_counter_q[intf][fu][$clog2(NrWordsPerVector*ELENB)-1:0] >> MAXEW) != vs2_vreg_addr[$clog2(NrWordsPerVector)-1:0];
pending_index[intf][fu] = (mem_idx_counter_q[intf][fu][$clog2(NrWordsPerVector*ELENB)-1:0] >> MAXEW) != vs2_vreg_addr[intf][$clog2(NrWordsPerVector)-1:0];
end
end: gen_mem_req_addr_intf_fu
end: gen_mem_req_addr_intf

// Calculate the register file addresses
always_comb begin : gen_vreg_addr
for (genvar intf = 0; intf < NrInterfaces; intf++) begin : gen_vreg_addr_intf
vd_vreg_addr[intf] = (commit_insn_q.vd << $clog2(NrWordsPerVector)) + ($unsigned(vd_elem_id) << 1) + intf;
vs2_vreg_addr[intf] = (mem_spatz_req.vs2 << $clog2(NrWordsPerVector)) + ($unsigned(vs2_elem_id_q) << 1) + intf;
for (int intf = 0; intf < NrInterfaces; intf++) begin : gen_vreg_addr_intf
vd_vreg_addr[intf] = (commit_insn_q.vd << $clog2(NrWordsPerVector)) + ($unsigned(vd_elem_id[intf]) << 1) + intf;
vs2_vreg_addr[intf] = (mem_spatz_req.vs2 << $clog2(NrWordsPerVector)) + ($unsigned(vs2_elem_id_q[intf]) << 1) + intf;
end
end

Expand Down Expand Up @@ -617,6 +618,9 @@ module spatz_vlsu
vrf_req_t [NrInterfaces-1:0] vrf_req_d, vrf_req_q;
logic [NrInterfaces-1:0] vrf_req_valid_d, vrf_req_ready_d;
logic [NrInterfaces-1:0] vrf_req_valid_q, vrf_req_ready_q;
logic [NrInterfaces-1:0] vrf_req_q_rsp_valid_q;
logic [NrInterfaces-1:0] vrf_commit_intf_valid;
logic vrf_commit_all_intf_valid;

for (genvar intf = 0; intf < NrInterfaces; intf++) begin : gen_vrf_req_register_intf
spill_register #(
Expand Down Expand Up @@ -647,7 +651,7 @@ module spatz_vlsu

// Ack when the vector store finishes, or when the vector load commits to the VRF.
// With more than an interface, we need to wait until all the interfaces commit to the VRF.
assign vlsu_rsp_o = &vrf_commit_intf_valid && |vrf_req_valid_q ? vrf_req_q.rsp : '{id: commit_insn_q.id, default: '0};
assign vlsu_rsp_o = &vrf_commit_intf_valid && |vrf_req_valid_q ? vrf_req_q[0].rsp : '{id: commit_insn_q.id, default: '0};
assign vlsu_rsp_valid_o = &vrf_commit_intf_valid && |vrf_req_valid_q ? |vrf_req_ready_q : vlsu_finished_req && !commit_insn_q.is_load;

//////////////
Expand All @@ -666,7 +670,7 @@ module spatz_vlsu

for (genvar intf = 0; intf < NrInterfaces; intf++) begin: gen_vreg_counter_proc
for (genvar fu = 0; fu < N_FU; fu++) begin: gen_vreg_counter_proc
automatic int unsigned port = intf * N_FU + fu;
localparam int unsigned port = intf * N_FU + fu;

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[verible-verilog-lint] hw/ip/spatz/src/spatz_vlsu.sv#L673 

Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]
Raw output 
message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]" location:{path:"hw/ip/spatz/src/spatz_vlsu.sv" range:{start:{line:673 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

// The total amount of vector bytes we have to work through
vlen_t max_bytes;
Expand Down Expand Up @@ -697,14 +701,14 @@ module spatz_vlsu
end

for (genvar intf = 0; intf < NrInterfaces; intf++) begin: gen_vd_elem_id
assign vd_elem_id[intf] = (commit_counter_q[intf*N_FU] > vreg_start_0)
? commit_counter_q[intf*N_FU] >> $clog2(ELENB)
: commit_counter_q[((intf+1)*N_FU)-1] >> $clog2(ELENB);
assign vd_elem_id[intf] = (commit_counter_q[intf][0] > vreg_start_0)
? commit_counter_q[intf][0] >> $clog2(ELENB)
: commit_counter_q[intf][3] >> $clog2(ELENB);
end

for (genvar intf = 0; intf < NrInterfaces; intf++) begin: gen_mem_counter_proc_intf
for (genvar fu = 0; fu < N_FU; fu++) begin: gen_mem_counter_proc_intf_fu
automatic int unsigned port = intf * N_FU + fu;
localparam int unsigned port = intf * N_FU + fu;

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[verible-verilog-lint] hw/ip/spatz/src/spatz_vlsu.sv#L711 

Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]
Raw output 
message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]" location:{path:"hw/ip/spatz/src/spatz_vlsu.sv" range:{start:{line:711 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

// The total amount of vector bytes we have to work through
vlen_t max_bytes;
Expand Down Expand Up @@ -833,8 +837,10 @@ module spatz_vlsu

// Count which vs2 element we should load (indexed loads)
vs2_elem_id_d = vs2_elem_id_q;
if (&(pending_index ^ ~mem_operation_valid) && mem_is_indexed)
vs2_elem_id_d = vs2_elem_id_q + 1;
for (int intf = 0; intf < NrInterfaces; intf++) begin
if (&(pending_index[intf] ^ ~mem_operation_valid[intf]) && mem_is_indexed)
vs2_elem_id_d[intf] = vs2_elem_id_q[intf] + 1;
end
if (mem_spatz_req_ready)
vs2_elem_id_d = '0;

Expand All @@ -847,7 +853,7 @@ module spatz_vlsu
vrf_req_valid_d[intf] = &(rob_rvalid[intf] | ~mem_pending[intf]) && |mem_pending[intf];

for (int unsigned fu = 0; fu < N_FU; fu++) begin
automatic unsigned int port = intf * N_FU + fu;
automatic int unsigned port = intf * N_FU + fu;

automatic logic [63:0] data = rob_rdata[intf][fu];

Expand Down Expand Up @@ -928,7 +934,7 @@ module spatz_vlsu
`endif
if (!rob_full[intf][fu] && !offset_queue_full[intf][fu] && mem_operation_valid[intf][fu]) begin
rob_req_id[intf][fu] = spatz_mem_req_ready[intf][fu] & spatz_mem_req_valid[intf][fu];
mem_req_lvalid[intf][fu] = (!mem_is_indexed || (vrf_rvalid_i[1] && !pending_index[intf][fu])) && mem_spatz_req.op_mem.is_load;
mem_req_lvalid[intf][fu] = (!mem_is_indexed || (vrf_rvalid_i[intf][1] && !pending_index[intf][fu])) && mem_spatz_req.op_mem.is_load;
mem_req_id[intf][fu] = rob_id[intf][fu];
mem_req_last[intf][fu] = mem_operation_last[intf][fu];
end
Expand All @@ -942,9 +948,9 @@ module spatz_vlsu
for (int unsigned fu = 0; fu < N_FU; fu++) begin
automatic int unsigned port = intf * N_FU + fu;

rob_wdata[intf][fu] = vrf_rdata_i[0][ELEN*port +: ELEN];
rob_wdata[intf][fu] = vrf_rdata_i[intf][0][ELEN*port +: ELEN];
rob_wid[intf][fu] = rob_id[intf][fu];
rob_req_id[intf][fu] = vrf_rvalid_i[0] && (!mem_is_indexed || vrf_rvalid_i[1]);
rob_req_id[intf][fu] = vrf_rvalid_i[intf][0] && (!mem_is_indexed || vrf_rvalid_i[intf][1]);
rob_push[intf][fu] = rob_req_id[intf][fu];
end
end
Expand Down Expand Up @@ -995,7 +1001,7 @@ module spatz_vlsu
default: mem_req_data[intf][fu] = data;
endcase

mem_req_svalid[intf][fu] = rob_rvalid[intf][fu] && (!mem_is_indexed || (vrf_rvalid_i[1] && !pending_index[intf][fu])) && !mem_spatz_req.op_mem.is_load;
mem_req_svalid[intf][fu] = rob_rvalid[intf][fu] && (!mem_is_indexed || (vrf_rvalid_i[intf][1] && !pending_index[intf][fu])) && !mem_spatz_req.op_mem.is_load;
mem_req_id[intf][fu] = rob_rid[intf][fu];
mem_req_last[intf][fu] = mem_operation_last[intf][fu];
rob_pop[intf][fu] = spatz_mem_req_valid[intf][fu] && spatz_mem_req_ready[intf][fu];
Expand Down Expand Up @@ -1028,8 +1034,7 @@ module spatz_vlsu
// Create memory requests
for (genvar intf = 0; intf < NrInterfaces; intf++) begin : gen_mem_req
for (genvar fu = 0; fu < N_FU; fu++) begin : gen_mem_req
genvar port;
port = intf * N_FU + fu;
localparam int unsigned port = intf * N_FU + fu;

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[verible-verilog-lint] hw/ip/spatz/src/spatz_vlsu.sv#L1037 

Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]
Raw output 
message:"Non-type localparam names must be styled with CamelCase [Style: constants] [parameter-name-style]" location:{path:"hw/ip/spatz/src/spatz_vlsu.sv" range:{start:{line:1037 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}

spill_register #(
.T(spatz_mem_req_t)
Expand Down

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