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DMA integration #5

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1 change: 1 addition & 0 deletions .github/workflows/lint.yml
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,7 @@ jobs:
./rtl/tb/riscv_pkg.sv
./rtl/tb/tb_fs_handler.sv
./rtl/safety_island_bootrom_carfield.sv
./rtl/dma/safety_island_dma_generated.sv
extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal"
github_token: ${{ secrets.GITHUB_TOKEN }}
reviewdog_reporter: github-check
Expand Down
35 changes: 27 additions & 8 deletions Bender.lock
Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,8 @@ packages:
dependencies:
- common_cells
axi:
revision: fccffb5953ec8564218ba05e20adbedec845e014
version: 0.39.1
revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6
version: 0.39.3
source:
Git: https://github.com/pulp-platform/axi.git
dependencies:
Expand All @@ -33,6 +33,13 @@ packages:
- axi
- common_cells
- common_verification
axi_stream:
revision: 54891ff40455ca94a37641b9da4604647878cc07
version: 0.1.1
source:
Git: https://github.com/pulp-platform/axi_stream.git
dependencies:
- common_cells
clic:
revision: 3aa6f06eb03e6c74b6fead5b1d42318f49a3cf32
version: 3.0.0-rc1
Expand All @@ -42,8 +49,8 @@ packages:
- common_cells
- register_interface
common_cells:
revision: 2bd027cb87eaa9bf7d17196ec5f69864b35b630f
version: 1.32.0
revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb
version: 1.37.0
source:
Git: https://github.com/pulp-platform/common_cells.git
dependencies:
Expand Down Expand Up @@ -79,9 +86,21 @@ packages:
Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
dependencies:
- common_cells
idma:
revision: d8d4b25a6ab8a7b654aa14d304ee5f508860be81
version: null
source:
Git: https://github.com/pulp-platform/idma.git
dependencies:
- axi
- axi_stream
- common_cells
- common_verification
- obi
- register_interface
obi:
revision: d04f1706ba5b7731bbc0a3a085e725e29fcc5b8e
version: 0.1.1
revision: c2141a653c755461ff44f61d12aeb5d99fc8e760
version: 0.1.3
source:
Git: https://github.com/pulp-platform/obi.git
dependencies:
Expand All @@ -98,8 +117,8 @@ packages:
- register_interface
- tech_cells_generic
register_interface:
revision: d7693be4aef1fc7e7eb2b00b41c42e87d959866c
version: 0.4.2
revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
version: 0.4.4
source:
Git: https://github.com/pulp-platform/register_interface.git
dependencies:
Expand Down
11 changes: 7 additions & 4 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -8,21 +8,22 @@ package:
- "Michael Rogenmoser <[email protected]>"

dependencies:
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.37.0 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3 }
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.1 }
redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: "6a011b6" } # `hmr-alt` branch
riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 }
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.12 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.1 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 }
cv32e40p: { git: "https://github.com/pulp-platform/cv32e40p.git", rev: "1a93f34" } # `michaero/safety-island-clic` branch
clic: { git: "https://github.com/pulp-platform/clic.git", rev: "3aa6f06" } # `aottaviano/dev` branch
fpnew: { git: "https://github.com/pulp-platform/cvfpu.git", rev: pulp-v0.1.3 }
apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.3 }
timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 }
obi: { git: "https://github.com/pulp-platform/obi.git", version: 0.1.1 }
obi: { git: "https://github.com/pulp-platform/obi.git", version: 0.1.3 }
unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 }
axi_obi: { path: "future/axi_obi" }
idma: { git: "https://github.com/pulp-platform/idma.git", rev: d8d4b25a6ab8a7b654aa14d304ee5f508860be81 } # requires #53

sources:
# Level 1
Expand All @@ -35,11 +36,13 @@ sources:
files:
- rtl/safety_island_bootrom.sv
- rtl/cv32e40p_fpu_wrap.sv
- rtl/dma/safety_island_dma_generated.sv
- target: simulation
files:
- rtl/tb/tb_fs_handler.sv
- rtl/tb/riscv_pkg.sv
# Level 2
- rtl/dma/safety_island_dma.sv
- rtl/safety_core_wrap.sv
- rtl/soc_ctrl/safety_soc_ctrl_reg_top.sv
# Level 3
Expand Down
1 change: 1 addition & 0 deletions requirements.txt
Original file line number Diff line number Diff line change
Expand Up @@ -2,3 +2,4 @@ hjson
mako
pyyaml
tabulate
flatdict
219 changes: 219 additions & 0 deletions rtl/dma/safety_island_dma.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,219 @@
// Copyright 2024 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51

// Authors:
// - Michael Rogenmoser <[email protected]>

`include "idma/typedef.svh"
`include "obi/typedef.svh"

module safety_island_dma import safety_island_pkg::*; #(
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic,

/// OBI Request and Response channel type
parameter obi_pkg::obi_cfg_t ObiCfg = obi_pkg::ObiDefaultConfig,
parameter type obi_a_chan_t = logic,
parameter type obi_r_chan_t = logic,
parameter type obi_req_t = logic,
parameter type obi_rsp_t = logic
) (
input logic clk_i,
input logic rst_ni,
input logic test_mode_i,

/// Register configuration ports
input reg_req_t reg_req_i,
output reg_rsp_t reg_rsp_o,

// OBI ports
output obi_req_t [1:0] obi_req_o,
input obi_rsp_t [1:0] obi_rsp_i
);

localparam int unsigned TFLenWidth = 24;

`IDMA_TYPEDEF_FULL_REQ_T(idma_req_t,
logic[ObiCfg.IdWidth-1:0],
logic[ObiCfg.AddrWidth-1:0],
logic[TFLenWidth-1:0])
`IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, logic[ObiCfg.AddrWidth-1:0])

typedef struct packed {
obi_a_chan_t a_chan;
logic [0:0] padding;
} obi_read_a_chan_padded_t;

typedef union packed {
obi_read_a_chan_padded_t obi;
} read_meta_channel_t;

typedef struct packed {
obi_a_chan_t a_chan;
logic [0:0] padding;
} obi_write_a_chan_padded_t;

typedef union packed {
obi_write_a_chan_padded_t obi;
} write_meta_channel_t;

`OBI_TYPEDEF_REQ_T(internal_obi_req_t, obi_a_chan_t)

idma_req_t backend_req;
idma_rsp_t backend_rsp;
logic backend_req_valid,
backend_req_ready,
backend_rsp_valid,
backend_rsp_ready;

idma_pkg::idma_busy_t backend_busy;

logic [31:0] next_id, completed_id;

internal_obi_req_t [1:0] internal_obi_req, internal_obi_req_spill;
obi_rsp_t [1:0] internal_obi_rsp, internal_obi_rsp_spill;

// reg_frontend
idma_reg32_1d #(
.NumRegs ( 1 ),
.NumStreams ( 1 ),
.IdCounterWidth ( 32 ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.dma_req_t ( idma_req_t )
) i_frontend (
.clk_i,
.rst_ni,
.dma_ctrl_req_i( reg_req_i ),
.dma_ctrl_rsp_o( reg_rsp_o ),
.dma_req_o ( backend_req ),
.req_valid_o ( backend_req_valid ),
.req_ready_i ( backend_req_ready ),
.next_id_i ( next_id ),
.stream_idx_o (),
.done_id_i ( completed_id ),
.busy_i ( backend_busy ),
.midend_busy_i ('0)
);

idma_transfer_id_gen #(
.IdWidth ( 32 )
) i_transfer_id_gen (
.clk_i,
.rst_ni,

.issue_i ( backend_req_valid & backend_req_ready ),
.retire_i ( backend_rsp_valid ),
.next_o ( next_id ),
.completed_o( completed_id )
);

assign backend_rsp_ready = 1'b1;

// Backend
idma_backend_rw_obi #(
.DataWidth ( ObiCfg.DataWidth ),
.AddrWidth ( ObiCfg.AddrWidth ),
.UserWidth ( 1 ), // unused internally, needs >0
.AxiIdWidth ( ObiCfg.IdWidth ),
.NumAxInFlight ( 3 ),
.BufferDepth ( 3 ),
.TFLenWidth ( TFLenWidth ),
.MemSysDepth ( 3 ),
.CombinedShifter ( 1'b0 ),
.RAWCouplingAvail ( 1'b0 ),
.MaskInvalidData ( 1'b1 ),
.HardwareLegalizer ( 1'b1 ),
.RejectZeroTransfers ( 1'b1 ),
.ErrorCap ( idma_pkg::NO_ERROR_HANDLING ),
.PrintFifoInfo ( 1'b0 ),
.idma_req_t ( idma_req_t ),
.idma_rsp_t ( idma_rsp_t ),
.idma_eh_req_t ( idma_pkg::idma_eh_req_t ),
.idma_busy_t ( idma_pkg::idma_busy_t ),
.obi_req_t ( internal_obi_req_t ),
.obi_rsp_t ( obi_rsp_t ),
.read_meta_channel_t ( read_meta_channel_t ),
.write_meta_channel_t( write_meta_channel_t )
) i_backend (
.clk_i,
.rst_ni,
.testmode_i ( test_mode_i ),

.idma_req_i ( backend_req ),
.req_valid_i ( backend_req_valid ),
.req_ready_o ( backend_req_ready ),

.idma_rsp_o ( backend_rsp ),
.rsp_valid_o ( backend_rsp_valid ),
.rsp_ready_i ( backend_rsp_ready ),

.idma_eh_req_i ( '0 ),
.eh_req_valid_i ( '0 ),
.eh_req_ready_o (),

.obi_read_req_o ( internal_obi_req[0] ),
.obi_read_rsp_i ( internal_obi_rsp[0] ),

.obi_write_req_o( internal_obi_req[1] ),
.obi_write_rsp_i( internal_obi_rsp[1] ),

.busy_o ( backend_busy )
);

for (genvar i = 0; i < 2; i++) begin : gen_rready_convert
spill_register #(
.T (obi_a_chan_t ),
.Bypass ( '0 )
) i_spill_a (
.clk_i,
.rst_ni,
.valid_i (internal_obi_req[i].req),
.ready_o (internal_obi_rsp[i].gnt),
.data_i (internal_obi_req[i].a),
.valid_o (internal_obi_req_spill[i].req),
.ready_i (internal_obi_rsp_spill[i].gnt),
.data_o (internal_obi_req_spill[i].a)
);

spill_register #(
.T (obi_r_chan_t ),
.Bypass ( '0 )
) i_spill_r (
.clk_i,
.rst_ni,
.valid_i (internal_obi_rsp_spill[i].rvalid),
.ready_o (internal_obi_req_spill[i].rready),
.data_i (internal_obi_rsp_spill[i].r),
.valid_o (internal_obi_rsp[i].rvalid),
.ready_i (internal_obi_req[i].rready),
.data_o (internal_obi_rsp[i].r)
);

obi_rready_converter #(
.obi_a_chan_t( obi_a_chan_t ),
.obi_r_chan_t( obi_r_chan_t ),
.Depth ( 2 ),
.CombRspReq ( 1'b1 )
) i_obi_rready_converter (
.clk_i,
.rst_ni,
.test_mode_i,

.sbr_a_chan_i( internal_obi_req_spill[i].a ),
.req_i ( internal_obi_req_spill[i].req ),
.gnt_o ( internal_obi_rsp_spill[i].gnt ),
.sbr_r_chan_o( internal_obi_rsp_spill[i].r ),
.rvalid_o ( internal_obi_rsp_spill[i].rvalid ),
.rready_i ( internal_obi_req_spill[i].rready ),

.mgr_a_chan_o( obi_req_o[i].a ),
.req_o ( obi_req_o[i].req ),
.gnt_i ( obi_rsp_i[i].gnt ),
.mgr_r_chan_i( obi_rsp_i[i].r ),
.rvalid_i ( obi_rsp_i[i].rvalid )
);
end

endmodule
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