Add clearer icache parameter descriptions

pulp-platform · Aug 22, 2024 · 92272ba · 92272ba
1 parent 65ecffa
commit 92272ba
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Showing 2 changed files with 22 additions and 8 deletions.
diff --git a/rtl/safety_island_pkg.sv b/rtl/safety_island_pkg.sv
@@ -150,4 +150,19 @@ package safety_island_pkg;
   // Cores do not support more than 2 outstanding transactions
   localparam int unsigned AxiMaxOutTrans = 2;
 
+  // Cache configuration
+  // Number of lines in L0 - one for current, one for prefetch
+  localparam int unsigned ICacheL0LineCount = 2;
+  // Line Width
+  localparam int unsigned ICacheLineWidth = 128;
+  // Number of L1 lines
+  localparam int unsigned ICacheLineCount = 32;
+  // Number of cache ways
+  localparam int unsigned ICacheWayCount = 4;
+  // Serial lookup (tag then data)
+  localparam bit ICacheSerialLookup = 1'b1;
+  // Use standard cells for L1 tag
+  localparam bit ICacheL1TagScm = 1'b1;
+
+
 endpackage
diff --git a/rtl/safety_island_top.sv b/rtl/safety_island_top.sv
@@ -16,8 +16,7 @@
 `include "apb/typedef.svh"
 
 module safety_island_top import safety_island_pkg::*; #(
-  parameter safety_island_pkg::safety_island_cfg_t SafetyIslandCfg =
-            safety_island_pkg::SafetyIslandDefaultConfig,
+  parameter safety_island_cfg_t        SafetyIslandCfg = SafetyIslandDefaultConfig,
 
   parameter  int unsigned              GlobalAddrWidth = 32,
   parameter  bit [GlobalAddrWidth-1:0] BaseAddr        = 32'h0000_0000,
@@ -523,18 +522,18 @@ module safety_island_top import safety_island_pkg::*; #(
 
     obi_icache_wrap #(
       .NumFetchPorts     ( 1 ),
-      .L0LineCount       ( 2 ),
-      .LineWidth         ( 128 ),
-      .LineCount         ( 32 ),
-      .WayCount          ( 4 ),
+      .L0LineCount       ( ICacheL0LineCount ),
+      .LineWidth         ( ICacheLineWidth ),
+      .LineCount         ( ICacheLineCount ),
+      .WayCount          ( ICacheWayCount ),
       .FetchAddrWidth    ( 32 ),
       .FetchDataWidth    ( DataWidth ),
       .AxiAddrWidth      ( AxiAddrWidth ),
       .AxiDataWidth      ( AxiDataWidth ),
       .FetchPriority     ( 1'b1 ),
       .MergeFetches      ( 1'b0 ), // No fetches to merge as only single core
-      .SerialLookup      ( 1'b1 ),
-      .L1TagScm          ( 1'b1 ),
+      .SerialLookup      ( ICacheSerialLookup ),
+      .L1TagScm          ( ICacheL1TagScm ),
       .NumAxiOutstanding ( 2 ), // One fetch, one prefetch
       .EarlyLatch        ( 1'b0 ),
       .L0EarlyTagWidth   ( -1 ),