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Merge pull request #3 from pulp-platform/michaero/ci
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Add CI
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@micprog
micprog authored Jul 5, 2024
2 parents 1cc316a + 87fd170 commit 8e090e3
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30 changes: 30 additions & 0 deletions .github/workflows/internal.yml
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# Copyright 2024 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51

# Author: Michael Rogenmoser <[email protected]>

name: internal

on:
push:
branches: [ main ]
pull_request:
branches: [ main ]
workflow_dispatch:

jobs:
gitlab-ci:
runs-on: ubuntu-latest
steps:
- name: Mirror and check
uses: pulp-platform/pulp-actions/gitlab-ci@v2
# Skip on forks or pull requests from forks due to missing secrets.
if: >
github.repository == 'pulp-platform/safety_island' &&
(github.event_name != 'pull_request' ||
github.event.pull_request.head.repo.full_name == github.repository)
with:
domain: iis-git.ee.ethz.ch
repo: github-mirror/safety_island
token: ${{ secrets.GITLAB_TOKEN }}
72 changes: 72 additions & 0 deletions .github/workflows/lint.yml
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# Copyright 2024 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51

# Author: Michael Rogenmoser <[email protected]>

name: lint

on:
push:
branches: [ main ]
pull_request:
branches: [ main ]
workflow_dispatch:

jobs:
check-stale:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v4
- uses: actions/setup-python@v5
with:
python-version: '3.9'
cache: 'pip'
- name: Install Bender
uses: pulp-platform/pulp-actions/bender-install@v2
- name: Python Requirements
run: pip install -r requirements.txt
- name: Check clean make targets
# bootrom todo, toolchain required
run: |
make safed-hw-gen
git status && test -z "$(git status --porcelain)"
lint-verilog:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v4
- uses: chipsalliance/verible-linter-action@main
with:
paths: |
./rtl
./future/axi_obi/src
exclude_paths: |
./rtl/soc_ctrl/safety_soc_ctrl_reg_pkg.sv
./rtl/soc_ctrl/safety_soc_ctrl_reg_top.sv
./rtl/tb/jtag_pkg.sv
./rtl/tb/riscv_pkg.sv
./rtl/tb/tb_fs_handler.sv
./rtl/safety_island_bootrom_carfield.sv
extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal"
github_token: ${{ secrets.GITHUB_TOKEN }}
reviewdog_reporter: github-check

# lint-license:
# runs-on: ubuntu-latest
# steps:
# - name: Checkout
# uses: actions/checkout@v3
# - name: Check license
# uses: pulp-platform/pulp-actions/lint-license@v2
# with:
# license: |
# Copyright (\d{4}(-\d{4})?\s)?(\(C\)\s)?(ETH Zurich and University of Bologna|lowRISC contributors|ETH Zurich|ETH Zurich, University of Bologna and GreenWaves Technologies)(.)?
# ((Solderpad Hardware License, Version 0.51|Licensed under the Apache License, Version 2.0), see LICENSE for details.|\
# Copyright and related rights are licensed under the Solderpad Hardware|\
# Licensed under the Apache License, Version 2.0 \(the \"License\"\);)
# (SPDX-License-Identifier: (SHL-0.51|Apache-2.0)|\
# License, Version 0.51 \(the \"License\"\); you may not use this file except in|\
# you may not use this file except in compliance with the License.)
# # Exclude generated headers (no license checker support for optional lines)
# exclude_paths:
8 changes: 4 additions & 4 deletions boot/gen_rom.py
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Expand Up @@ -48,8 +48,8 @@

module = """\
module $module_name #(
parameter ADDR_WIDTH=32,
parameter DATA_WIDTH=32
parameter int unsigned ADDR_WIDTH=32,
parameter int unsigned DATA_WIDTH=32
) (
input logic CLK,
input logic RST_N,
Expand All @@ -58,10 +58,10 @@
output logic [DATA_WIDTH-1:0] Q
);
localparam NUM_WORDS = 2**ADDR_WIDTH;
localparam int unsigned NumWords = 2**ADDR_WIDTH;
logic [ADDR_WIDTH-1:0] A_Q;
const logic [DATA_WIDTH-1:0] MEM[NUM_WORDS] = {
const logic [DATA_WIDTH-1:0] MEM[NumWords] = {
$content
};
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33 changes: 20 additions & 13 deletions future/axi_obi/src/axi_to_detailed_mem_user.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -456,7 +456,7 @@ module axi_to_detailed_mem_user #(
region: mem_req.region
};

for (genvar i = 0; i < NumBanks; i++) begin
for (genvar i = 0; i < NumBanks; i++) begin : gen_atop_assign
assign mem_atop_o [i] = banked_req_atop[i].atop;
assign mem_lock_o [i] = banked_req_atop[i].lock;
assign mem_id_o [i] = banked_req_atop[i].id;
Expand All @@ -468,7 +468,7 @@ module axi_to_detailed_mem_user #(
end

logic [NumBanks-1:0][RUserExtra+2-1:0] tmp_ersp, bank_ersp;
for (genvar i = 0; i < NumBanks; i++) begin
for (genvar i = 0; i < NumBanks; i++) begin : gen_err_assign
assign mem_rdata.err[i] = tmp_ersp[i][0];
assign mem_rdata.exokay[i] = tmp_ersp[i][1];
assign mem_rdata.ruser[i] = tmp_ersp[i][RUserExtra+2-1:2];
Expand Down Expand Up @@ -538,24 +538,27 @@ module axi_to_detailed_mem_user #(
.ready_i ({axi_req_i.b_ready, axi_req_i.r_ready })
);

localparam NumBytesPerBank = DataWidth/NumBanks/8;
localparam int unsigned NumBytesPerBank = DataWidth/NumBanks/8;

logic [NumBanks-1:0] meta_buf_bank_strb, meta_buf_size_enable;
logic resp_b_err, resp_b_exokay, resp_r_err, resp_r_exokay;

// Collect `err` and `exokay` from all banks
// To ensure correct propagation, `err` is grouped with `OR` and `exokay` is grouped with `AND`.
for (genvar i = 0; i < NumBanks; i++) begin
for (genvar i = 0; i < NumBanks; i++) begin : gen_meta_buf
// Set active write banks based on strobe
assign meta_buf_bank_strb[i] = |meta_buf.strb[i*NumBytesPerBank +: NumBytesPerBank];
// Set active read banks based on size and address offset: (bank.end > addr) && (bank.start < addr+size)
assign meta_buf_size_enable[i] = ((i*NumBytesPerBank + NumBytesPerBank) > (meta_buf.addr % DataWidth/8)) &&
((i*NumBytesPerBank) < ((meta_buf.addr % DataWidth/8) + 1<<meta_buf.size));
// Set active read banks based on size and address offset:
// (bank.end > addr) && (bank.start < addr+size)
assign meta_buf_size_enable[i] =
((i*NumBytesPerBank + NumBytesPerBank) > (meta_buf.addr % DataWidth/8)) &&
((i*NumBytesPerBank) < ((meta_buf.addr % DataWidth/8) + 1<<meta_buf.size));
end
assign resp_b_err = |(m2s_resp.err & meta_buf_bank_strb); // Ensure only active banks are used (strobe)
assign resp_b_exokay = &(m2s_resp.exokay | ~meta_buf_bank_strb); // Ensure only active banks are used (strobe)
assign resp_r_err = |(m2s_resp.err & meta_buf_size_enable); // Ensure only active banks are used (size & addr offset)
assign resp_r_exokay = &(m2s_resp.exokay | ~meta_buf_size_enable); // Ensure only active banks are used (size & addr offset)
// Ensure only active banks are used
assign resp_b_err = |(m2s_resp.err & meta_buf_bank_strb); // strobe
assign resp_b_exokay = &(m2s_resp.exokay | ~meta_buf_bank_strb); // strobe
assign resp_r_err = |(m2s_resp.err & meta_buf_size_enable); // size & addr offset
assign resp_r_exokay = &(m2s_resp.exokay | ~meta_buf_size_enable); // size & addr offset

logic collect_b_err_d, collect_b_err_q;
logic collect_b_exokay_d, collect_b_exokay_q;
Expand Down Expand Up @@ -585,7 +588,9 @@ module axi_to_detailed_mem_user #(
// Compose B responses.
assign axi_resp_o.b = '{
id: meta_buf.id,
resp: next_collect_b_err ? axi_pkg::RESP_SLVERR : next_collect_b_exokay ? axi_pkg::RESP_EXOKAY : axi_pkg::RESP_OKAY,
resp: next_collect_b_err ?
axi_pkg::RESP_SLVERR :
next_collect_b_exokay ? axi_pkg::RESP_EXOKAY : axi_pkg::RESP_OKAY,
user: ruser_i
};

Expand All @@ -594,7 +599,9 @@ module axi_to_detailed_mem_user #(
data: m2s_resp.data,
id: meta_buf.id,
last: meta_buf.last,
resp: resp_r_err ? axi_pkg::RESP_SLVERR : resp_r_exokay ? axi_pkg::RESP_EXOKAY : axi_pkg::RESP_OKAY,
resp: resp_r_err ?
axi_pkg::RESP_SLVERR :
resp_r_exokay ? axi_pkg::RESP_EXOKAY : axi_pkg::RESP_OKAY,
user: ruser_i
};

Expand Down
54 changes: 30 additions & 24 deletions future/axi_obi/src/axi_to_obi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -31,14 +31,17 @@ module axi_to_obi #(
parameter type axi_rsp_t = logic,
// Dependent Parameters, *DO NOT OVERWRITE*
parameter int unsigned NumBanks = AxiDataWidth/ObiCfg.DataWidth,
parameter int unsigned AUserWidthAdjusted = ObiCfg.OptionalCfg.AUserWidth ? ObiCfg.OptionalCfg.AUserWidth : 1,
parameter int unsigned WUserWidthAdjusted = ObiCfg.OptionalCfg.WUserWidth ? ObiCfg.OptionalCfg.WUserWidth : 1,
parameter int unsigned RUserWidthAdjusted = ObiCfg.OptionalCfg.RUserWidth ? ObiCfg.OptionalCfg.RUserWidth : 1
parameter int unsigned AUserWidthAdjusted = ObiCfg.OptionalCfg.AUserWidth ?
ObiCfg.OptionalCfg.AUserWidth : 1,
parameter int unsigned WUserWidthAdjusted = ObiCfg.OptionalCfg.WUserWidth ?
ObiCfg.OptionalCfg.WUserWidth : 1,
parameter int unsigned RUserWidthAdjusted = ObiCfg.OptionalCfg.RUserWidth ?
ObiCfg.OptionalCfg.RUserWidth : 1
) (
input logic clk_i,
input logic rst_ni,
input logic testmode_i,

input axi_req_t axi_req_i,
output axi_rsp_t axi_rsp_o,

Expand Down Expand Up @@ -82,6 +85,8 @@ module axi_to_obi #(
axi_req_t axi_read_req, axi_write_req;
axi_rsp_t axi_read_rsp, axi_write_rsp;

localparam int unsigned IdRuserWidth = ObiCfg.IdWidth+ObiCfg.OptionalCfg.RUserWidth;

logic [2*NumBanks-1:0] bank_mem_req;
logic [2*NumBanks-1:0] bank_mem_gnt;
logic [2*NumBanks-1:0][ AxiAddrWidth-1:0] bank_mem_addr;
Expand All @@ -98,9 +103,9 @@ module axi_to_obi #(
logic [2*NumBanks-1:0][ ObiCfg.DataWidth-1:0] bank_mem_rdata;
logic [2*NumBanks-1:0] bank_mem_err;
logic [2*NumBanks-1:0] bank_mem_exokay;
logic [2*NumBanks-1:0][ObiCfg.IdWidth+ObiCfg.OptionalCfg.RUserWidth-1:0] bank_mem_ruser;
logic [2*NumBanks-1:0][ IdRuserWidth-1:0] bank_mem_ruser;

logic [2*NumBanks-1:0][ObiCfg.IdWidth+ObiCfg.OptionalCfg.RUserWidth-1:0] rsp_ruser;
logic [2*NumBanks-1:0][ IdRuserWidth-1:0] rsp_ruser;
logic [ NumBanks-1:0][2*AxiUserWidth-1:0] tmp_write_user;

obi_req_t [2*NumBanks-1:0] obi_reqs;
Expand Down Expand Up @@ -141,13 +146,13 @@ module axi_to_obi #(
.HideStrb ( 1'b1 ),
.OutFifoDepth( 2 ),
.PropagateWUser ( 1'b0 ),
.RUserExtra (ObiCfg.IdWidth+ObiCfg.OptionalCfg.RUserWidth)
.RUserExtra (IdRuserWidth)
) i_axi_to_mem_read (
.clk_i,
.rst_ni,

.busy_o (),

.axi_req_i ( axi_read_req ),
.axi_resp_o ( axi_read_rsp ),

Expand Down Expand Up @@ -196,13 +201,13 @@ module axi_to_obi #(
.HideStrb ( 1'b1 ),
.OutFifoDepth( 2 ),
.PropagateWUser(1'b1),
.RUserExtra (ObiCfg.IdWidth+ObiCfg.OptionalCfg.RUserWidth)
.RUserExtra (IdRuserWidth)
) i_axi_to_mem_write (
.clk_i,
.rst_ni,

.busy_o (),

.axi_req_i ( axi_write_req ),
.axi_resp_o ( axi_write_rsp ),

Expand Down Expand Up @@ -239,14 +244,13 @@ module axi_to_obi #(
assign bank_mem_id [2*NumBanks-1:NumBanks] = req_write_aid_i;
assign bank_mem_user [2*NumBanks-1:NumBanks] = req_write_auser_i;

for (genvar i = 0; i < NumBanks; i++) begin
for (genvar i = 0; i < NumBanks; i++) begin : gen_user_rid
assign req_w_user_o[i] = tmp_write_user[i][2*AxiUserWidth-1:AxiUserWidth];
assign req_aw_user_o[i] = tmp_write_user[i][AxiUserWidth-1:0];
assign rsp_read_rid_o [i] = rsp_ruser[ i][ObiCfg.IdWidth-1:0];
assign rsp_read_ruser_o [i] = rsp_ruser[ i][ObiCfg.IdWidth+ObiCfg.OptionalCfg.RUserWidth-1:ObiCfg.IdWidth];
assign rsp_read_ruser_o [i] = rsp_ruser[ i][IdRuserWidth-1:ObiCfg.IdWidth];
assign rsp_write_rid_o [i] = rsp_ruser[NumBanks+i][ObiCfg.IdWidth-1:0];
assign rsp_write_ruser_o[i] = rsp_ruser[NumBanks+i][ObiCfg.IdWidth+ObiCfg.OptionalCfg.RUserWidth-1:ObiCfg.IdWidth];

assign rsp_write_ruser_o[i] = rsp_ruser[NumBanks+i][IdRuserWidth-1:ObiCfg.IdWidth];
end

if (ObiCfg.OptionalCfg.UseAtop) begin : gen_atop
Expand All @@ -267,6 +271,7 @@ module axi_to_obi #(
axi_pkg::ATOP_SMAX: obi_atop[i] = obi_pkg::AMOMAX;
axi_pkg::ATOP_UMIN: obi_atop[i] = obi_pkg::AMOMINU;
axi_pkg::ATOP_UMAX: obi_atop[i] = obi_pkg::AMOMAXU;
default: ;
endcase
end
end
Expand All @@ -281,7 +286,8 @@ module axi_to_obi #(
assign obi_reqs[i].a.addr = bank_mem_addr[i];
if (ObiCfg.OptionalCfg.UseAtop) begin : gen_obi_bank_assign_atop
assign obi_reqs[i].a.a_optional.atop = obi_atop[i];
assign obi_reqs[i].a.wdata = (obi_atop[i] == obi_pkg::AMOAND) ? ~bank_mem_wdata[i] : bank_mem_wdata[i];
assign obi_reqs[i].a.wdata = (obi_atop[i] == obi_pkg::AMOAND) ?
~bank_mem_wdata[i] : bank_mem_wdata[i];
assign bank_mem_exokay[i] = obi_rsps[i].r.r_optional.exokay;
end else begin : gen_obi_bank_tie_atop
assign obi_reqs[i].a.wdata = bank_mem_wdata[i];
Expand All @@ -293,8 +299,8 @@ module axi_to_obi #(
assign bank_mem_rdata[i] = obi_rsps[i].r.rdata;
assign bank_mem_err[i] = obi_rsps[i].r.err;
assign bank_mem_ruser[i][ObiCfg.IdWidth-1:0] = obi_rsps[i].r.rid;
if (ObiCfg.OptionalCfg.RUserWidth) begin
assign bank_mem_ruser[i][ObiCfg.IdWidth+ObiCfg.OptionalCfg.RUserWidth-1:ObiCfg.IdWidth] = obi_rsps[i].r.r_optional.ruser;
if (ObiCfg.OptionalCfg.RUserWidth) begin : gen_ruser
assign bank_mem_ruser[i][IdRuserWidth-1:ObiCfg.IdWidth] = obi_rsps[i].r.r_optional.ruser;
end
if (ObiCfg.OptionalCfg.UseProt) begin : gen_obi_bank_assign_prot
assign obi_reqs[i].a.a_optional.prot[0] = ~bank_mem_prot[i][2];
Expand All @@ -306,15 +312,15 @@ module axi_to_obi #(
assign obi_reqs[i].a.a_optional.memtype[1] = ~bank_mem_cache[i][1];
end
assign obi_reqs[i].a.aid = bank_mem_id[i];
if (i < NumBanks) begin
if (ObiCfg.OptionalCfg.AUserWidth) begin
if (i < NumBanks) begin : gen_bank_auser
if (ObiCfg.OptionalCfg.AUserWidth) begin : gen_auser
assign obi_reqs[i].a.a_optional.auser = req_read_auser_i;
end
end else begin
if (ObiCfg.OptionalCfg.AUserWidth) begin
end else begin : gen_bank_awuser
if (ObiCfg.OptionalCfg.AUserWidth) begin : gen_auser
assign obi_reqs[i].a.a_optional.auser = req_write_auser_i;
end
if (ObiCfg.OptionalCfg.WUserWidth) begin
if (ObiCfg.OptionalCfg.WUserWidth) begin : gen_wuser
assign obi_reqs[i].a.a_optional.wuser = req_write_wuser_i;
end
end
Expand Down
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