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Add rready converter for backend
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@micprog
micprog committed Jul 8, 2024
1 parent e4f5754 commit 8c8a6de
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Showing 4 changed files with 48 additions and 13 deletions.
8 changes: 4 additions & 4 deletions Bender.lock
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Expand Up @@ -87,8 +87,8 @@ packages:
dependencies:
- common_cells
idma:
revision: 95f366e56f7e772c283fb3c8b343afc4a3978375
version: 0.6.2
revision: c12caf59bb482fe44b27361f6924ad346b2d22fe
version: 0.6.3
source:
Git: https://github.com/pulp-platform/idma.git
dependencies:
Expand All @@ -99,8 +99,8 @@ packages:
- obi
- register_interface
obi:
revision: 1aa411df145c4ebdd61f8fed4d003c33f7b20636
version: 0.1.2
revision: b3af63fe40121c0479f2e3c355cc88912a2e633d
version: null
source:
Git: https://github.com/pulp-platform/obi.git
dependencies:
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4 changes: 2 additions & 2 deletions Bender.yml
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Expand Up @@ -20,10 +20,10 @@ dependencies:
fpnew: { git: "https://github.com/pulp-platform/cvfpu.git", rev: pulp-v0.1.3 }
apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.3 }
timer_unit: { git: "https://github.com/pulp-platform/timer_unit.git", version: 1.0.2 }
obi: { git: "https://github.com/pulp-platform/obi.git", version: 0.1.1 }
obi: { git: "https://github.com/pulp-platform/obi.git", rev: b3af63fe40121c0479f2e3c355cc88912a2e633d }
unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 }
axi_obi: { path: "future/axi_obi" }
idma: { git: "https://github.com/pulp-platform/idma.git", version: 0.6.2 }
idma: { git: "https://github.com/pulp-platform/idma.git", version: 0.6.3 }

sources:
# Level 1
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48 changes: 41 additions & 7 deletions rtl/dma/safety_island_dma.sv
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Expand Up @@ -6,15 +6,16 @@
// - Michael Rogenmoser <[email protected]>

`include "idma/typedef.svh"
`include "obi/typedef.svh"

module safety_island_dma import safety_island_pkg::*; #(
// parameter safety_island_cfg_t SafetyIslandCfg = safety_island_pkg::SafetyIslandDefaultConfig,
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic,

/// OBI Request and Response channel type
parameter obi_pkg::obi_cfg_t ObiCfg = obi_pkg::ObiDefaultConfig,
parameter type obi_a_chan_t = logic,
parameter type obi_r_chan_t = logic,
parameter type obi_req_t = logic,
parameter type obi_rsp_t = logic
) (
Expand All @@ -33,7 +34,10 @@ module safety_island_dma import safety_island_pkg::*; #(

localparam int unsigned TFLenWidth = 24;

`IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, logic[ObiCfg.IdWidth-1:0], logic[ObiCfg.AddrWidth-1:0], logic[TFLenWidth-1:0])
`IDMA_TYPEDEF_FULL_REQ_T(idma_req_t,
logic[ObiCfg.IdWidth-1:0],
logic[ObiCfg.AddrWidth-1:0],
logic[TFLenWidth-1:0])
`IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, logic[ObiCfg.AddrWidth-1:0])

typedef struct packed {
Expand All @@ -54,6 +58,7 @@ module safety_island_dma import safety_island_pkg::*; #(
obi_write_a_chan_padded_t obi;
} write_meta_channel_t;

`OBI_TYPEDEF_REQ_T(internal_obi_req_t, obi_a_chan_t)

idma_req_t backend_req;
idma_rsp_t backend_rsp;
Expand All @@ -66,6 +71,9 @@ module safety_island_dma import safety_island_pkg::*; #(

logic [31:0] next_id, completed_id;

internal_obi_req_t internal_obi_req[1:0];

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] rtl/dma/safety_island_dma.sv#L74 

Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw output 
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]"  location:{path:"./rtl/dma/safety_island_dma.sv"  range:{start:{line:74  column:39}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
obi_rsp_t internal_obi_rsp[1:0];

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] rtl/dma/safety_island_dma.sv#L75 

Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]
Raw output 
message:"Unpacked dimension range must be declared in big-endian ([0:N-1]) order.  Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]"  location:{path:"./rtl/dma/safety_island_dma.sv"  range:{start:{line:75  column:39}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}

// reg_frontend
idma_reg32_1d #(
.NumRegs ( 1 ),
Expand Down Expand Up @@ -124,7 +132,7 @@ module safety_island_dma import safety_island_pkg::*; #(
.idma_rsp_t ( idma_rsp_t ),
.idma_eh_req_t ( idma_pkg::idma_eh_req_t ),
.idma_busy_t ( idma_pkg::idma_busy_t ),
.obi_req_t ( obi_req_t ),
.obi_req_t ( internal_obi_req_t ),
.obi_rsp_t ( obi_rsp_t ),
.read_meta_channel_t ( read_meta_channel_t ),
.write_meta_channel_t( write_meta_channel_t )
Expand All @@ -145,13 +153,39 @@ module safety_island_dma import safety_island_pkg::*; #(
.eh_req_valid_i ( '0 ),
.eh_req_ready_o (),

.obi_read_req_o ( obi_req_o[0] ),
.obi_read_rsp_i ( obi_rsp_i[0] ),
.obi_read_req_o ( internal_obi_req[0] ),
.obi_read_rsp_i ( internal_obi_rsp[0] ),

.obi_write_req_o( obi_req_o[1] ),
.obi_write_rsp_i( obi_rsp_i[1] ),
.obi_write_req_o( internal_obi_req[1] ),
.obi_write_rsp_i( internal_obi_rsp[1] ),

.busy_o ( backend_busy )
);

for (genvar i = 0; i < 2; i++) begin

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] rtl/dma/safety_island_dma.sv#L165 

All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output 
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]"  location:{path:"./rtl/dma/safety_island_dma.sv"  range:{start:{line:165  column:34}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
obi_rready_converter #(
.obi_a_chan_t( obi_a_chan_t ),
.obi_r_chan_t( obi_r_chan_t ),
.Depth ( 2 ),
.CombRspReq ( 1'b1 )
) i_obi_rready_converter (
.clk_i,
.rst_ni,
.test_mode_i,

.sbr_a_chan_i( internal_obi_req[i].a ),
.req_i ( internal_obi_req[i].req ),
.gnt_o ( internal_obi_rsp[i].gnt ),
.sbr_r_chan_o( internal_obi_rsp[i].r ),
.rvalid_o ( internal_obi_rsp[i].rvalid ),
.rready_i ( internal_obi_req[i].rready ),

.mgr_a_chan_o( obi_req_o[i].a ),
.req_o ( obi_req_o[i].req ),
.gnt_i ( obi_rsp_i[i].gnt ),
.mgr_r_chan_i( obi_rsp_i[i].r ),
.rvalid_i ( obi_rsp_i[i].rvalid )
);
end

endmodule
1 change: 1 addition & 0 deletions rtl/safety_island_top.sv
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Expand Up @@ -619,6 +619,7 @@ module safety_island_top import safety_island_pkg::*; #(
.reg_rsp_t ( safety_reg_rsp_t ),
.ObiCfg ( MgrObiCfg ),
.obi_a_chan_t( mgr_obi_a_chan_t ),
.obi_r_chan_t( mgr_obi_r_chan_t ),
.obi_req_t ( mgr_obi_req_t ),
.obi_rsp_t ( mgr_obi_rsp_t )
) i_dma_unit (
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