Cleanup of ECC modules & SRAM

.github/waiver.verible

@@ -0,0 +1,5 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+waive --rule=explicit-parameter-storage-type --location="./rtl/ecc_wrap/ecc_sram.sv"

.github/workflows/ci.yml

@@ -53,6 +53,6 @@ jobs:
             ./rtl/ODRG_unit/odrg_manager_reg_top.sv
             ./rtl/pulpissimo_tcls/tcls_manager_reg_pkg.sv
             ./rtl/pulpissimo_tcls/tcls_manager_reg_top.sv
-          extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal --waiver_files util/waiver.verible"
+          extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal --waiver_files .github/waiver.verible"
           github_token: ${{ secrets.GITHUB_TOKEN }}
           reviewdog_reporter: github-check

Bender.yml

@@ -4,10 +4,10 @@ package:
     - "Michael Rogenmoser <[email protected]>"
 
 dependencies:
-  tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
+  tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 }
   common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
-  register_interface:  { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 }
-  common_cells:        { git: "https://github.com/pulp-platform/common_cells.git", version: 1.24.0 }
+  register_interface:  { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 }
+  common_cells:        { git: "https://github.com/pulp-platform/common_cells.git", version: 1.35.0 }
 
 sources:
     # Source files grouped in levels. Files in level 0 have no dependencies on files in this
@@ -69,7 +69,10 @@ sources:
     # Level 2
   - rtl/bitwise_TMR_voter.sv
   - rtl/ecc_wrap/ecc_manager.sv
-  - rtl/ecc_wrap/ecc_sram_wrap.sv
+  - target: deprecated
+    files:
+      - rtl/ecc_wrap/ecc_sram_wrap.sv
+  - rtl/ecc_wrap/ecc_sram.sv
     # Level 3
   - include_dirs:
       - rtl/ODRG_unit

Makefile

@@ -31,21 +31,18 @@ TARGET_DIR_ECC = rtl/ecc_wrap
 .PHONY: gen_ODRG gen_TCLS gen_ecc_registers gen_ECC
 gen_ODRG:
 	python $(REG_TOOL) $(HJSON_ODRG) -t $(TARGET_DIR_ODRG) -r
-	python $(REG_TOOL) $(HJSON_ODRG) -d > $(TARGET_DIR_ODRG)/doc.html
+	python $(REG_TOOL) $(HJSON_ODRG) -d > $(TARGET_DIR_ODRG)/doc.md
 	python $(REG_TOOL) $(HJSON_ODRG) -D > $(TARGET_DIR_ODRG)/ODRG.h
-	python $(REG_TOOL) $(HJSON_ODRG) --doc > $(TARGET_DIR_ODRG)/doc.md
 
 gen_TCLS:
 	python $(REG_TOOL) $(HJSON_TCLS) -t $(TARGET_DIR_TCLS) -r
-	python $(REG_TOOL) $(HJSON_TCLS) -d > $(TARGET_DIR_TCLS)/doc.html
+	python $(REG_TOOL) $(HJSON_TCLS) -d > $(TARGET_DIR_TCLS)/doc.md
 	python $(REG_TOOL) $(HJSON_TCLS) -D > $(TARGET_DIR_TCLS)/TCLS.h
-	python $(REG_TOOL) $(HJSON_TCLS) --doc > $(TARGET_DIR_TCLS)/doc.md
 
 gen_ecc_registers:
 	python $(REG_TOOL) $(HJSON_ECC) -t $(TARGET_DIR_ECC) -r
-	python $(REG_TOOL) $(HJSON_ECC) -d > $(TARGET_DIR_ECC)/doc.html
+	python $(REG_TOOL) $(HJSON_ECC) -d > $(TARGET_DIR_ECC)/doc.md
 	python $(REG_TOOL) $(HJSON_ECC) -D > $(TARGET_DIR_ECC)/ECC.h
-	python $(REG_TOOL) $(HJSON_ECC) --doc > $(TARGET_DIR_ECC)/doc.md
 
 gen_ECC:
 	$(BENDER) vendor init

requirements.txt

@@ -1,3 +1,4 @@
 hjson
 mako
 pyyaml
+tabulate