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Fix verilog ling.
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Yvan Tortorella committed Feb 17, 2024
1 parent 30114e9 commit ff72826
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3 changes: 3 additions & 0 deletions .github/workflows/lint.yml
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Expand Up @@ -46,6 +46,9 @@ jobs:
github_token: ${{ secrets.GITHUB_TOKEN }}
fail_on_error: true
reviewdog_reporter: github-check
exclude: |
./rtl/redmule_noncomp.sv
./rtl/redmule_fma.sv
lint-cxx:
runs-on: ubuntu-latest
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69 changes: 36 additions & 33 deletions rtl/redmule_scheduler.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -134,7 +134,7 @@ logic [1:0] transfer_count_d,
logic [31:0] x_rows_offs_d,
x_rows_offs_q,
x_cols_offs_d,
x_cols_offs_q;
x_cols_offs_q;
logic [15:0] w_loaded_d, w_loaded_q,
w_iters_d, w_iters_q,
tot_w_loaded_d, tot_w_loaded_q,
Expand All @@ -150,7 +150,7 @@ logic [$clog2(H):0] h_shift_d,
d_shift_d,
d_shift_q;
logic w_cols_lftovr_en,
w_cols_lftovr_rst,
w_cols_lftovr_rst,
x_cols_lftovr_en,
x_cols_lftovr_rst;
logic [$clog2(D):0] w_cycles_q,
Expand All @@ -169,49 +169,52 @@ fpnew_pkg::fp_format_e input_cast_src_fmt ,
localparam int unsigned JMP = NumByte*(DATA_W/MemDw - 1);
localparam int unsigned NBYTES = BITW/8;

typedef enum logic [3:0] {ENGINE_IDLE, PRELOAD_Y, LOAD_Y, X_REQ, W_REQ, STORE_REQ, FIRST_LOAD, WAIT, WAIT_ONE, WAIT_TWO, LOAD_X, LOAD_W, STORE, SKIP_W} redmule_fsm_state;
redmule_fsm_state current, next;
typedef enum logic [3:0] {ENGINE_IDLE, PRELOAD_Y, LOAD_Y, X_REQ, W_REQ, STORE_REQ, FIRST_LOAD, WAIT,
WAIT_ONE, WAIT_TWO, LOAD_X, LOAD_W, STORE, SKIP_W} redmule_fsm_state_e;
redmule_fsm_state_e current, next;

always_comb begin : address_gen_signals
// Here we initialize the streamer source signals
// Here we initialize the streamer source signals
// for the X stream source
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[X_ADDR] + x_rows_offs_q + x_cols_offs_q;
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.tot_len = (x_rows_lftovr_q == 0) ? W : x_rows_lftovr_q;
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d0_len = 32'd1;
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d0_stride = 32'd0;
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d1_len = W;
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d1_stride = reg_file_i.hwpe_params[X_D1_STRIDE];
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d2_stride = '0;
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[X_ADDR]
+ x_rows_offs_q + x_cols_offs_q;

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L180 

Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:180  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.tot_len = (x_rows_lftovr_q == 0) ?
W : x_rows_lftovr_q;
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d0_len = 'd1;
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d0_stride = 'd0;
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d1_len = W;
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d1_stride = reg_file_i.hwpe_params[X_D1_STRIDE];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L186 

Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:186  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.d2_stride = '0;
cntrl_streamer_o.x_stream_source_ctrl.addressgen_ctrl.dim_enable_1h = 2'b11;
// Here we initialize the streamer source signals
// for the W stream source
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[W_ADDR];
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[W_TOT_LEN];
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d0_len = reg_file_i.hwpe_params[W_ITERS][31:16];
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d0_stride = reg_file_i.hwpe_params[W_D0_STRIDE];
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d1_len = reg_file_i.hwpe_params[W_ITERS][15:0];
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d1_stride = JMP;
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d2_stride = 32'd0;
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[W_ADDR];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L191 

Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:191  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[W_TOT_LEN];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L192 

Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:192  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d0_len = reg_file_i.hwpe_params[W_ITERS][31:16];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L193 

Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:193  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d0_stride = reg_file_i.hwpe_params[W_D0_STRIDE];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L194 

Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:194  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d1_len = reg_file_i.hwpe_params[W_ITERS][15:0];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L195 

Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:195  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d1_stride = JMP;
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.d2_stride = 'd0;
cntrl_streamer_o.w_stream_source_ctrl.addressgen_ctrl.dim_enable_1h = 2'b11;
// Here we initialize the streamer source signals
// for the Y stream source
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[Z_ADDR];
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[Z_TOT_LEN];
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d0_len = W;
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d0_stride = reg_file_i.hwpe_params[Z_D0_STRIDE];
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d1_len = reg_file_i.hwpe_params[W_ITERS][15:0];
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d1_stride = JMP;
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d2_stride = reg_file_i.hwpe_params[Z_D2_STRIDE];
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[Z_ADDR];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L201 

Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:201  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[Z_TOT_LEN];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L202 

Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:202  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d0_len = W;
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d0_stride = reg_file_i.hwpe_params[Z_D0_STRIDE];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L204 

Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:204  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d1_len = reg_file_i.hwpe_params[W_ITERS][15:0];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L205 

Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:205  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d1_stride = JMP;

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L206 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:206  column:75}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:206  column:75}  end:{line:207}}  text:"    cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d1_stride = JMP;\n"}
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.d2_stride = reg_file_i.hwpe_params[Z_D2_STRIDE];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L207 

Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:207  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.y_stream_source_ctrl.addressgen_ctrl.dim_enable_1h = 2'b11;
// Here we initialize the streamer sink signals for
// the Z stream sink
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[Z_ADDR];
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[Z_TOT_LEN];
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d0_len = W;
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d0_stride = reg_file_i.hwpe_params[Z_D0_STRIDE];
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d1_len = reg_file_i.hwpe_params[W_ITERS][15:0];
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d1_stride = JMP;
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d2_stride = reg_file_i.hwpe_params[Z_D2_STRIDE];
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.base_addr = reg_file_i.hwpe_params[Z_ADDR];
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.tot_len = reg_file_i.hwpe_params[Z_TOT_LEN];
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d0_len = W;
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d0_stride = reg_file_i.hwpe_params[Z_D0_STRIDE];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L214 

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:214  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d1_len = reg_file_i.hwpe_params[W_ITERS][15:0];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L215 

Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:215  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d1_stride = JMP;
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.d2_stride = reg_file_i.hwpe_params[Z_D2_STRIDE];

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[verible-verilog-lint] rtl/redmule_scheduler.sv#L217 

Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output 
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]"  location:{path:"rtl/redmule_scheduler.sv"  range:{start:{line:217  column:101}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
cntrl_streamer_o.z_stream_sink_ctrl.addressgen_ctrl.dim_enable_1h = 2'b11;
end

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