doc: Add generated mid-ends

pulp-platform · Mar 11, 2024 · 5071ea1 · 5071ea1
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diff --git a/doc/src/index.rst b/doc/src/index.rst
@@ -49,11 +49,13 @@ The morty docs provide the generated description of the SystemVerilog files with
 
   `RW_AXI Backend <idma_backend_synth_rw_axi/index.html>`_
 
+
 .. image:: ../fig/graph/idma_backend_synth_r_axi_w_obi.png
   :width: 600
 
 .. image:: ../fig/graph/idma_backend_synth_r_obi_w_axi.png
   :width: 600
 
 .. image:: ../fig/graph/idma_backend_synth_rw_axi.png
-  :width: 600
+  :width: 600
+
diff --git a/doc/src/midend.rst b/doc/src/midend.rst
@@ -1,13 +1,11 @@
-iDMA Midend
-===========
-
-Parameters
-----------
-
-+------------------+------------------+---------------------------------------------------------------------+
-| Parameter        | Type             | Description                                                         |
-+==================+==================+=====================================================================+
-| ``Instantiated`` | ``bit``          | Optional enable for the midend (default only supports 1D transfers) |
-+------------------+------------------+---------------------------------------------------------------------+
-| ``Dimensions``   | ``unsigned int`` | Number of dimensions supported (2-8)                                |
-+------------------+------------------+---------------------------------------------------------------------+
+iDMA Midends
+============
+
+Morty files:
+
+.. only:: html
+
+  `ND Backend <idma_nd_midend_synth/index.html>`_
+
+.. image:: ../fig/graph/idma_nd_midend_synth.png
+  :width: 600