Move protocol assigns and checkers to their repos

Bender.lock

@@ -15,6 +15,13 @@ packages:
     - common_cells
     - common_verification
     - tech_cells_generic
+  axi_stream:
+    revision: 54891ff40455ca94a37641b9da4604647878cc07
+    version: 0.1.1
+    source:
+      Git: https://github.com/pulp-platform/axi_stream.git
+    dependencies:
+    - common_cells
   common_cells:
     revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239
     version: 1.33.0
@@ -29,6 +36,14 @@ packages:
     source:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
+  obi:
+    revision: 416d109497cd68d99277f1f1887a038329b3eac8
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/obi.git
+    dependencies:
+    - common_cells
+    - common_verification
   register_interface:
     revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19
     version: 0.4.3

Bender.yml

@@ -14,10 +14,12 @@ package:
     - "Axel Vanoni <[email protected]>"
 
 dependencies:
+  axi:                 { git: "https://github.com/pulp-platform/axi.git",                 version: 0.39.1 }
+  axi_stream:          { git: "https://github.com/pulp-platform/axi_stream.git",          version: 0.1.1  }
   common_cells:        { git: "https://github.com/pulp-platform/common_cells.git",        version: 1.33.0 }
   common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3  }
-  axi:                 { git: "https://github.com/pulp-platform/axi.git",                 version: 0.39.1 }
   register_interface:  { git: "https://github.com/pulp-platform/register_interface.git",  version: 0.4.3  }
+  obi:                 { git: "https://github.com/pulp-platform/obi.git",                 rev: idma_content-tbenz  }
 
 export_include_dirs:
   - src/include
@@ -111,7 +113,6 @@ sources:
       - test/frontend/tb_idma_desc64_top.sv
       - test/frontend/tb_idma_desc64_bench.sv
       - test/future/idma_tb_per2axi.sv
-      - test/future/idma_obi_asserter.sv
       - test/future/TLToAXI4.v
       - test/midend/tb_idma_nd_midend.sv
       - test/midend/tb_idma_rt_midend.sv

idma.mk

@@ -112,33 +112,34 @@ define idma_gen
 	$(PYTHON) $(IDMA_GEN) --entity $1 --tpl $2 --db $3 --ids $4 --fids $5 > $6
 endef
 
-$(IDMA_RTL_DIR)/idma_transport_layer_%.sv: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_ROOT)/src/backend/tpl/idma_transport_layer.sv.tpl
+$(IDMA_RTL_DIR)/idma_transport_layer_%.sv: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_ROOT)/src/backend/tpl/idma_transport_layer.sv.tpl $(IDMA_DB_FILES)
 	$(call idma_gen,transport,$(IDMA_ROOT)/src/backend/tpl/idma_transport_layer.sv.tpl,$(IDMA_DB_FILES),$*,,$@)
 
-$(IDMA_RTL_DIR)/idma_legalizer_%.sv: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_ROOT)/src/backend/tpl/idma_legalizer.sv.tpl
+$(IDMA_RTL_DIR)/idma_legalizer_%.sv: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_ROOT)/src/backend/tpl/idma_legalizer.sv.tpl $(IDMA_DB_FILES)
 	$(call idma_gen,legalizer,$(IDMA_ROOT)/src/backend/tpl/idma_legalizer.sv.tpl,$(IDMA_DB_FILES),$*,,$@)
 
-$(IDMA_RTL_DIR)/idma_backend_%.sv: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_RTL_DIR)/idma_legalizer_%.sv $(IDMA_RTL_DIR)/idma_transport_layer_%.sv $(IDMA_ROOT)/src/backend/tpl/idma_backend.sv.tpl
+$(IDMA_RTL_DIR)/idma_backend_%.sv: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_RTL_DIR)/idma_legalizer_%.sv $(IDMA_RTL_DIR)/idma_transport_layer_%.sv $(IDMA_ROOT)/src/backend/tpl/idma_backend.sv.tpl $(IDMA_DB_FILES)
 	$(call idma_gen,backend,$(IDMA_ROOT)/src/backend/tpl/idma_backend.sv.tpl,$(IDMA_DB_FILES),$*,,$@)
 
-$(IDMA_RTL_DIR)/idma_backend_synth_%.sv: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_RTL_DIR)/idma_backend_%.sv $(IDMA_ROOT)/src/backend/tpl/idma_backend_synth.sv.tpl
+$(IDMA_RTL_DIR)/idma_backend_synth_%.sv: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_RTL_DIR)/idma_backend_%.sv $(IDMA_ROOT)/src/backend/tpl/idma_backend_synth.sv.tpl $(IDMA_DB_FILES)
 	$(call idma_gen,synth_wrapper,$(IDMA_ROOT)/src/backend/tpl/idma_backend_synth.sv.tpl,$(IDMA_DB_FILES),$*,,$@)
 
-$(IDMA_RTL_DIR)/tb_idma_backend_%.sv: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_RTL_DIR)/idma_backend_%.sv $(IDMA_ROOT)/test/tpl/tb_idma_backend.sv.tpl
+$(IDMA_RTL_DIR)/tb_idma_backend_%.sv: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_RTL_DIR)/idma_backend_%.sv $(IDMA_ROOT)/test/tpl/tb_idma_backend.sv.tpl $(IDMA_DB_FILES)
 	$(call idma_gen,testbench,$(IDMA_ROOT)/test/tpl/tb_idma_backend.sv.tpl,$(IDMA_DB_FILES),$*,,$@)
 
 $(IDMA_VSIM_DIR)/wave/backend_%.do: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_RTL_DIR)/tb_idma_backend_%.sv $(IDMA_VSIM_DIR)/wave/tpl/backend.do.tpl
 	$(call idma_gen,vsim_wave,$(IDMA_VSIM_DIR)/wave/tpl/backend.do.tpl,$(IDMA_DB_FILES),$*,,$@)
 
-$(IDMA_RTL_DIR)/include/idma/tracer.svh: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_ROOT)/src/include/idma/tpl/tracer.svh.tpl $(IDMA_DB_FILES) $(IDMA_ROOT)/idma.mk
+$(IDMA_RTL_DIR)/include/idma/tracer.svh: $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_ROOT)/src/include/idma/tpl/tracer.svh.tpl $(IDMA_DB_FILES) $(IDMA_ROOT)/idma.mk $(IDMA_DB_FILES)
 	mkdir -p $(IDMA_RTL_DIR)/include/idma
 	$(call idma_gen,tracer,$(IDMA_ROOT)/src/include/idma/tpl/tracer.svh.tpl,$(IDMA_DB_FILES),$(IDMA_BACKEND_IDS),$(IDMA_FE_IDS),$@)
 
 idma_rtl_clean:
-	rm -f $(IDMA_RTL_DIR)/Bender.yml
-	rm -f $(IDMA_RTL_DIR)/*.sv
-	rm -f $(IDMA_VSIM_DIR)/wave/*.do
-	rm -f $(IDMA_RTL_DIR)/include/idma/tracer.svh
+	rm -f  $(IDMA_RTL_DIR)/Bender.yml
+	rm -f  $(IDMA_RTL_DIR)/*.sv
+	rm -f  $(IDMA_VSIM_DIR)/wave/*.do
+	rm -f  $(IDMA_RTL_DIR)/include/idma/tracer.svh
+	rm -rf $(IDMA_RTL_DIR)/include/idma
 
 # assemble the required files
 IDMA_INCLUDE_ALL += $(IDMA_RTL_DIR)/include/idma/tracer.svh
@@ -199,6 +200,7 @@ idma_reg_clean:
 	rm -f  $(IDMA_RTL_DIR)/*_reg_top.sv
 	rm -f  $(IDMA_RTL_DIR)/*_reg_pkg.sv
 	rm -f  $(IDMA_RTL_DIR)/Bender.yml
+	rm -f  $(IDMA_RTL_DIR)/*.hjson
 	rm -f  $(IDMA_REG_CUST_ALL)
 
 # assemble the required files

src/backend/idma_obi_read.sv

@@ -82,8 +82,8 @@ module idma_obi_read #(
     //--------------------------------------
     // connect the ar requests to the OBI bus
     assign read_req_o.a      = read_meta_req_i.obi.a_chan;
-    assign read_req_o.a_req  = read_meta_valid_i;
-    assign read_meta_ready_o = read_rsp_i.a_gnt;
+    assign read_req_o.req    = read_meta_valid_i;
+    assign read_meta_ready_o = read_rsp_i.gnt;
 
     //--------------------------------------
     // Mask pre-calculation
@@ -117,24 +117,24 @@ module idma_obi_read #(
     // the buffer can be pushed to if all the masked FIFO buffers (mask_in) are ready.
     assign in_ready = &(buffer_in_ready_i | ~mask_in);
     // the read can accept data if the buffer is ready and the response channel is ready
-    assign read_req_o.r_ready = in_ready & r_dp_ready_i;
+    assign read_req_o.rready = in_ready & r_dp_ready_i;
 
     // once valid data is applied, it can be pushed in all the selected (mask_in) buffers
     // be sure the response channel is ready
-    assign in_valid          = read_rsp_i.r_valid & in_ready & r_dp_ready_i;
+    assign in_valid          = read_rsp_i.rvalid & in_ready & r_dp_ready_i;
     assign buffer_in_valid_o = in_valid ? mask_in : '0;
 
     // r_dp_ready_o is triggered by the last element arriving from the read
-    assign r_dp_ready_o   = r_dp_valid_i & r_dp_ready_i & read_rsp_i.r_valid & in_ready;
-    assign r_chan_ready_o = read_req_o.r_ready;
-    assign r_chan_valid_o = read_rsp_i.r_valid;
+    assign r_dp_ready_o   = r_dp_valid_i & r_dp_ready_i & read_rsp_i.rvalid & in_ready;
+    assign r_chan_ready_o = read_req_o.rready;
+    assign r_chan_valid_o = read_rsp_i.rvalid;
 
     // connect r_dp response payload
-    assign r_dp_rsp_o.resp  = '0;
+    assign r_dp_rsp_o.resp  = {1'b0, read_rsp_i.r.err};
     assign r_dp_rsp_o.last  = 1'b1;
     assign r_dp_rsp_o.first = 1'b1;
 
     // r_dp_valid_o is triggered once the last element is here or an error occurs
-    assign r_dp_valid_o = read_rsp_i.r_valid & in_ready;
+    assign r_dp_valid_o = read_rsp_i.rvalid & in_ready;
 
 endmodule

src/backend/idma_obi_write.sv

@@ -104,13 +104,13 @@ module idma_obi_write #(
     assign buffer_clean = &(~buffer_out_valid_i);
 
     // write happening: both the bus (w_ready) and the buffer (ready_to_write) is high
-    assign write_happening = ready_to_write & write_rsp_i.a_gnt;
+    assign write_happening = ready_to_write & write_rsp_i.gnt;
 
     // the main buffer is conditionally to the write mask popped
     assign buffer_out_ready_o = write_happening ? mask_out : '0;
 
     // signal the bus that we are ready
-    assign write_req_o.a_req = ready_to_write;
+    assign write_req_o.req = ready_to_write;
 
     // connect data and strobe either directly or mask invalid data
     if (MaskInvalidData) begin : gen_mask_invalid_data
@@ -160,10 +160,10 @@ module idma_obi_write #(
     assign w_dp_rsp_o = '0;
 
     // w_dp_valid_o is triggered once the write answer is here
-    assign w_dp_valid_o = write_rsp_i.r_valid;
+    assign w_dp_valid_o = write_rsp_i.rvalid;
 
     // create back pressure on the b channel if the higher parts of the DMA cannot accept more
     // write responses
-    assign write_req_o.r_ready = w_dp_ready_i;
+    assign write_req_o.rready = w_dp_ready_i;
 
 endmodule

src/backend/tpl/idma_backend_synth.sv.tpl

@@ -7,7 +7,10 @@
 // - Tobias Senti <tsenti@ethz.ch>
 
 `include "axi/typedef.svh"
+`include "axi_stream/typedef.svh"
 `include "idma/typedef.svh"
+`include "obi/typedef.svh"
+`include "tilelink/typedef.svh"
 
 /// Synthesis wrapper for the iDMA backend. Unpacks all the interfaces to simple logic vectors
 module idma_backend_synth_${name_uniqueifier} #(

src/db/idma_axi_stream.yml

@@ -18,10 +18,10 @@ read_slave: "false"
 passive_req: "true"
 meta_channel_width: "localparam int unsigned axis_t_chan_width = $bits(axis_t_chan_t);"
 typedefs: |
-    `IDMA_AXI_STREAM_TYPEDEF_S_CHAN_T(axis_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t)
+    `AXI_STREAM_TYPEDEF_S_CHAN_T(axis_t_chan_t, data_t, strb_t, strb_t, id_t, id_t, user_t)
 
-    `IDMA_AXI_STREAM_TYPEDEF_REQ_T(axis_req_t, axis_t_chan_t)
-    `IDMA_AXI_STREAM_TYPEDEF_RSP_T(axis_rsp_t)
+    `AXI_STREAM_TYPEDEF_REQ_T(axis_req_t, axis_t_chan_t)
+    `AXI_STREAM_TYPEDEF_RSP_T(axis_rsp_t)
 read_bridge_template: |
     // AXI Stream to OBI Read Bridge
     obi_req_t axis_obi_read_req;
@@ -31,8 +31,8 @@ read_bridge_template: |
     assign axis_obi_read_req.a.wdata = '0;
     assign axis_obi_read_req.a.be    = '1;
 
-    assign axis_obi_read_req.r_ready = axis_read_rsp.tready;
-    assign axis_read_req.tvalid      = axis_obi_read_rsp.r_valid;
+    assign axis_obi_read_req.rready  = axis_read_rsp.tready;
+    assign axis_read_req.tvalid      = axis_obi_read_rsp.rvalid;
     always_comb begin
         axis_read_req.t      = '0;
         axis_read_req.t.data = axis_obi_read_rsp.r.rdata;
@@ -84,21 +84,21 @@ read_bridge_template: |
         while(axis_jobs.size() > 0) begin
             current_job = axis_jobs.pop_front();
             address = { current_job.src_addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} };
-            axis_obi_read_req.a_req = 1'b0;
+            axis_obi_read_req.req   = 1'b0;
             axis_obi_read_req.a.aid = current_job.id;
 
             // Wait for launch of job 
             wait(launched_axis_jobs > 0);
             launched_axis_jobs--;
             while(address < (current_job.src_addr + current_job.length)) begin
                 axis_obi_read_req.a.addr = address;
-                axis_obi_read_req.a_req  = 1'b1;
+                axis_obi_read_req.req  = 1'b1;
                 @(posedge clk);
-                if(axis_obi_read_rsp.a_gnt && axis_obi_read_req.a_req) begin
+                if(axis_obi_read_rsp.gnt && axis_obi_read_req.req) begin
                     address += StrbWidth;
                 end
             end
-            axis_obi_read_req.a_req  = 1'b0;
+            axis_obi_read_req.req  = 1'b0;
         end
     end
 
@@ -125,14 +125,14 @@ write_bridge_template: |
     obi_req_t axis_obi_write_req;
     obi_rsp_t axis_obi_write_rsp;
 
-    assign axis_obi_write_req.a_req   = axis_write_req.tvalid;
+    assign axis_obi_write_req.req     = axis_write_req.tvalid;
     assign axis_obi_write_req.a.we    = 1'b1;
     assign axis_obi_write_req.a.wdata = axis_write_req.t.data;
     assign axis_obi_write_req.a.be    = axis_write_req.t.keep;
     assign axis_obi_write_req.a.aid   = axis_write_req.t.id;
-    assign axis_obi_write_req.r_ready = 1'b1;
+    assign axis_obi_write_req.rready  = 1'b1;
 
-    assign axis_write_rsp.tready = axis_obi_write_rsp.a_gnt;
+    assign axis_write_rsp.tready = axis_obi_write_rsp.gnt;
 
     initial begin
         string job_file;

src/db/idma_obi.yml

@@ -18,11 +18,14 @@ read_slave: "false"
 passive_req: "false"
 meta_channel_width: "localparam int unsigned obi_a_chan_width = $bits(obi_a_chan_t);"
 typedefs: |
-    `IDMA_OBI_TYPEDEF_A_CHAN_T(obi_a_chan_t, addr_t, data_t, strb_t, id_t)
-    `IDMA_OBI_TYPEDEF_R_CHAN_T(obi_r_chan_t, data_t, id_t)
+    `OBI_TYPEDEF_MINIMAL_A_OPTIONAL(a_optional_t)
+    `OBI_TYPEDEF_MINIMAL_R_OPTIONAL(r_optional_t)
 
-    `IDMA_OBI_TYPEDEF_REQ_T(obi_req_t, obi_a_chan_t)
-    `IDMA_OBI_TYPEDEF_RESP_T(obi_rsp_t, obi_r_chan_t)
+    `OBI_TYPEDEF_TYPE_A_CHAN_T(obi_a_chan_t, addr_t, data_t, strb_t, id_t, a_optional_t)
+    `OBI_TYPEDEF_TYPE_R_CHAN_T(obi_r_chan_t, data_t, id_t, r_optional_t)
+
+    `OBI_TYPEDEF_REQ_T(obi_req_t, obi_a_chan_t)
+    `OBI_TYPEDEF_RSP_T(obi_rsp_t, obi_r_chan_t)
 bridge_template: |
     idma_obi2axi_bridge #(
         .DataWidth ( DataWidth    ),
@@ -47,15 +50,17 @@ legalizer_read_meta_channel: |
         be: '1,
         we: 1'b0,
         wdata: '0,
-        aid: opt_tf_q.axi_id
+        aid: opt_tf_q.axi_id,
+        a_optional: '0
     };
 legalizer_write_meta_channel: |
     w_req_o.aw_req.obi.a_chan = '{
         addr: { w_tf_q.addr[AddrWidth-1:OffsetWidth], {{OffsetWidth}{1'b0}} },
         be: '0,
         we: 1,
         wdata: '0,
-        aid: opt_tf_q.axi_id
+        aid: opt_tf_q.axi_id,
+        a_optional: '0
     };
 read_template: |
     idma_obi_read #(
@@ -138,39 +143,41 @@ synth_wrapper_ports_read: |
     input logic                    obi_read_rsp_r_valid_i,
     input data_t                   obi_read_rsp_r_rdata_i,
     input id_t                     obi_read_rsp_r_rid_i,
+    input logic                    obi_read_rsp_r_err_i,
 synth_wrapper_assign_write: |
-    assign obi_write_req_a_req_o   = obi_write_req.a_req;
+    assign obi_write_req_a_req_o   = obi_write_req.req;
     assign obi_write_req_a_addr_o  = obi_write_req.a.addr;
     assign obi_write_req_a_we_o    = obi_write_req.a.we;
     assign obi_write_req_a_be_o    = obi_write_req.a.be;
     assign obi_write_req_a_wdata_o = obi_write_req.a.wdata;
     assign obi_write_req_a_aid_o   = obi_write_req.a.aid;
-    assign obi_write_req_r_ready_o = obi_write_req.r_ready;
+    assign obi_write_req_r_ready_o = obi_write_req.rready;
 
-    assign obi_write_rsp.a_gnt   = obi_write_rsp_a_gnt_i;
-    assign obi_write_rsp.r_valid = obi_write_rsp_r_valid_i;
+    assign obi_write_rsp.gnt     = obi_write_rsp_a_gnt_i;
+    assign obi_write_rsp.rvalid  = obi_write_rsp_r_valid_i;
     assign obi_write_rsp.r.rdata = obi_write_rsp_r_rdata_i;
 synth_wrapper_assign_read: |
-    assign obi_read_req_a_req_o   = obi_read_req.a_req;
+    assign obi_read_req_a_req_o   = obi_read_req.req;
     assign obi_read_req_a_addr_o  = obi_read_req.a.addr;
     assign obi_read_req_a_we_o    = obi_read_req.a.we;
     assign obi_read_req_a_be_o    = obi_read_req.a.be;
     assign obi_read_req_a_wdata_o = obi_read_req.a.wdata;
-    assign obi_read_req_r_ready_o = obi_read_req.r_ready;
+    assign obi_read_req_r_ready_o = obi_read_req.rready;
 
-    assign obi_read_rsp.a_gnt   = obi_read_rsp_a_gnt_i;
-    assign obi_read_rsp.r_valid = obi_read_rsp_r_valid_i;
+    assign obi_read_rsp.gnt     = obi_read_rsp_a_gnt_i;
+    assign obi_read_rsp.rvalid  = obi_read_rsp_r_valid_i;
     assign obi_read_rsp.r.rdata = obi_read_rsp_r_rdata_i;
     assign obi_read_rsp.r.rid   = obi_read_rsp_r_rid_i;
+    assign obi_read_rsp.r.err   = obi_read_rsp_r_err_i;
 trace_signals:
     read:
         rsp:
-            valid: obi_read_req_o.a_req
-            ready: obi_read_rsp_i.a_gnt
+            valid: obi_read_req_o.req
+            ready: obi_read_rsp_i.gnt
             write_en: obi_read_req_o.a.we
     write:
         req:
-            valid: obi_write_req_o.a_req
-            ready: obi_write_rsp_i.a_gnt
+            valid: obi_write_req_o.req
+            ready: obi_write_rsp_i.gnt
             strobe: obi_write_req_o.a.be
             write_en: obi_write_req_o.a.we

src/db/idma_tilelink.yml

@@ -21,11 +21,11 @@ read_slave: "false"
 passive_req: "false"
 # logic[3:0] is the size field, is 4 bit as we're limited by the TLToAXI4 Bridge
 typedefs: |
-    `IDMA_TILELINK_TYPEDEF_A_CHAN_T(tilelink_a_chan_t, addr_t, data_t, strb_t, logic[3:0], logic[4:0])
-    `IDMA_TILELINK_TYPEDEF_D_CHAN_T(tilelink_d_chan_t, data_t, logic[3:0], logic[4:0], logic)
+    `TILELINK_TYPEDEF_A_CHAN_T(tilelink_a_chan_t, addr_t, data_t, strb_t, logic[3:0], logic[4:0])
+    `TILELINK_TYPEDEF_D_CHAN_T(tilelink_d_chan_t, data_t, logic[3:0], logic[4:0], logic)
 
-    `IDMA_TILELINK_TYPEDEF_REQ_T(tilelink_req_t, tilelink_a_chan_t)
-    `IDMA_TILELINK_TYPEDEF_RSP_T(tilelink_rsp_t, tilelink_d_chan_t)
+    `TILELINK_TYPEDEF_REQ_T(tilelink_req_t, tilelink_a_chan_t)
+    `TILELINK_TYPEDEF_RSP_T(tilelink_rsp_t, tilelink_d_chan_t)
 bridge_template: |
     idma_tilelink2axi_bridge #(
         .DataWidth      ( DataWidth      ),