snitch: Update desc64 front-end

.github/verible.waiver

@@ -4,3 +4,5 @@
 
 # Authors:
 # - Thomas Benz <[email protected]>
+
+waive --rule=package-filename --location="src/frontend/inst64/idma_inst64_opcode.sv"

Bender.yml

@@ -61,7 +61,13 @@ sources:
       - src/midend/idma_nd_midend.sv
       - src/midend/idma_rt_midend.sv
 
-  # Frontends (without inst64)
+  # RISC-V opcode package for ooc use of inst64
+  - target: all(rtl,snitch_cluster)
+    files:
+      # Level 0
+      - src/frontend/inst64/idma_inst64_snitch_pkg.sv
+
+  # Frontends
   - target: rtl
     files:
       # Level 0
@@ -71,8 +77,10 @@ sources:
       - src/frontend/desc64/idma_desc64_reader_gater.sv
       - src/frontend/desc64/idma_desc64_reshaper.sv
       - src/frontend/idma_transfer_id_gen.sv
+      - src/frontend/inst64/idma_inst64_events.sv
       # Level 1
       - src/frontend/desc64/idma_desc64_reg_wrapper.sv
+      - src/frontend/inst64/idma_inst64_top.sv
       # Level 2
       - src/frontend/desc64/idma_desc64_top.sv
 
@@ -90,7 +98,7 @@ sources:
       - src/midend/idma_rt_midend_synth.sv
 
   # Testbenches
-  - target: test
+  - target: idma_test
     files:
       # Level 0
       - test/frontend/tb_idma_desc64_top.sv

idma.mk

@@ -217,7 +217,7 @@ $(IDMA_PICKLE_DIR)/sources.json: $(IDMA_BENDER_FILES) $(IDMA_TB_ALL) $(IDMA_RTL_
 	$(BENDER) update
 	$(BENDER) checkout
 	mkdir -p $(IDMA_PICKLE_DIR)
-	$(BENDER) sources -f -t rtl -t synthesis -t synth -t asic | sed -e $(IDMA_RELATIVE_PATH_REGEX) > $@
+	$(BENDER) sources -f -t rtl -t synthesis -t synth -t asic -t snitch_cluster | sed -e $(IDMA_RELATIVE_PATH_REGEX) > $@
 
 $(IDMA_PICKLE_DIR)/%.sv: $(IDMA_PICKLE_DIR)/sources.json
 	$(MORTY) -f $< -i --top $* $(IDMA_MORTY_ARGS) --propagate_defines -o $@
@@ -284,7 +284,7 @@ endef
 $(IDMA_VSIM_DIR)/compile.tcl: $(IDMA_BENDER_FILES) $(IDMA_TB_ALL) $(IDMA_RTL_ALL)
 	$(BENDER) update
 	$(BENDER) checkout
-	$(call idma_generate_vsim, $@, -t sim -t test -t synth -t rtl -t asic,../../..)
+	$(call idma_generate_vsim, $@, -t sim -t test -t idma_test -t synth -t rtl -t asic -t snitch_cluster,../../..)
 
 idma_sim_clean:
 	rm -rf $(IDMA_VSIM_DIR)/compile.tcl
@@ -325,7 +325,7 @@ IDMA_VCS_PARAMS  ?=
 $(IDMA_VCS_DIR)/compile.sh: $(IDMA_BENDER_FILES) $(IDMA_TB_ALL) $(IDMA_RTL_ALL)
 	$(BENDER) update
 	$(BENDER) checkout
-	$(BENDER) script vcs -t test -t rtl -t synth -t simulation --vlog-arg "\$(IDMA_VLOGAN_ARGS)" --vlogan-bin "$(VLOGAN)" $(IDMA_VLOGAN_REL_PATHS) > $@
+	$(BENDER) script vcs -t test -t idma_test -t rtl -t synth -t simulation -t snitch_cluster --vlog-arg "\$(IDMA_VLOGAN_ARGS)" --vlogan-bin "$(VLOGAN)" $(IDMA_VLOGAN_REL_PATHS) > $@
 	chmod +x $@
 
 idma_vcs_compile: $(IDMA_VCS_DIR)/compile.sh

jobs/jobs.json

@@ -23,7 +23,7 @@
             "BufferDepth"         : 3,
             "TFLenWidth"          : 32,
             "MemSysDepth"         : 0,
-            "CombinedShifter"     : 0,
+            "CombinedShifter"     : 1,
             "MaskInvalidData"     : 1,
             "RAWCouplingAvail"    : 1,
             "HardwareLegalizer"   : 1,
@@ -122,7 +122,7 @@
             "BufferDepth"         : 3,
             "TFLenWidth"          : 32,
             "MemSysDepth"         : 0,
-            "CombinedShifter"     : 0,
+            "CombinedShifter"     : 1,
             "MaskInvalidData"     : 1,
             "RAWCouplingAvail"    : 0,
             "HardwareLegalizer"   : 1,
@@ -155,7 +155,7 @@
             "BufferDepth"         : 3,
             "TFLenWidth"          : 32,
             "MemSysDepth"         : 0,
-            "CombinedShifter"     : 0,
+            "CombinedShifter"     : 1,
             "MaskInvalidData"     : 1,
             "RAWCouplingAvail"    : 0,
             "HardwareLegalizer"   : 1,