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Fix JTAG VIP for dual-core initialization
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ricted98 committed Jan 9, 2025
1 parent bf65df4 commit 385c6ff
Showing 1 changed file with 1 addition and 2 deletions.
3 changes: 1 addition & 2 deletions target/sim/src/vip_cheshire_soc.sv
Original file line number Diff line number Diff line change
Expand Up @@ -342,13 +342,12 @@ module vip_cheshire_soc import cheshire_pkg::*; #(
// Write binary entry point in DM registers and set it as DPC
jtag_write(dm::Data1, entry[63:32]);
jtag_write(dm::Data0, entry[31:0]);
jtag_write(dm::Command, 32'h0033_07b1, 0, 1);
jtag_write(dm::Command, 32'h0033_07b1, 1, 1);
// Resume all harts
jtag_write(dm::DMControl, dm::dmcontrol_t'{resumereq: 1, dmactive: 1, hartsello: i, default: '0});
do jtag_dbg.read_dmi_exp_backoff(dm::DMStatus, status);
while (~status.allresumeack);
jtag_write(dm::DMControl, dm::dmcontrol_t'{resumereq: 0, dmactive: 1, hartsello: i, default: '0});
jtag_write(dm::Command, 32'h0, 0, 1);
$display("[JTAG] Resumed hart %d from 0x%h", i, entry);
end
endtask
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