Skip to content

Commit

Permalink
Create config files for different design targets.
Browse files Browse the repository at this point in the history
  • Loading branch information
Yvan Tortorella committed Jan 20, 2024
1 parent 6cddc52 commit afe2df1
Show file tree
Hide file tree
Showing 8 changed files with 132 additions and 107 deletions.
1 change: 1 addition & 0 deletions .github/workflows/lint.yml
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@ jobs:
uses: chipsalliance/verible-linter-action@main
with:
paths: hw
exclude_paths: hw/configs
extra_args: "--waiver_files .github/verible.waiver"
github_token: ${{ secrets.GITHUB_TOKEN }}
fail_on_error: true
Expand Down
5 changes: 5 additions & 0 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@ sources:
# package. Files in level 1 only depend on files in level 0, files in level 2 on files in
# levels 1 and 0, etc. Files within a level are ordered alphabetically.
# Level 0
- hw/configs/carfield_default_cfg.sv
- hw/carfield_cfg_pkg.sv
- hw/carfield_pkg.sv
- hw/regs/carfield_reg_pkg.sv
Expand Down Expand Up @@ -69,6 +70,10 @@ sources:
files:
- target/synth/carfield_synth_wrap.sv

- target: all(xilinx, fpga, xilinx_vanilla, xilinx_bd)
files:
- hw/configs/carfield_fpga_cfg.sv

- target: all(xilinx, fpga, xilinx_vanilla)
files:
- target/xilinx/src/cdc_dst_axi_err.sv
Expand Down
53 changes: 3 additions & 50 deletions hw/carfield.sv
Original file line number Diff line number Diff line change
Expand Up @@ -2045,7 +2045,7 @@ mailbox_unit #(
carfield_axi_slv_req_t axi_ethernet_req;
carfield_axi_slv_rsp_t axi_ethernet_rsp;

if (carfield_pkg::IslandsCfgDefault.EnEthernet) begin : gen_ethernet
if (CarfieldIslandsCfg.ethernet.enable) begin : gen_ethernet
axi_cdc_dst #(
.LogDepth ( LogDepth ),
.SyncStages ( SyncStages ),
Expand Down Expand Up @@ -2224,54 +2224,6 @@ if (carfield_pkg::IslandsCfgDefault.EnEthernet) begin : gen_ethernet

end else begin : gen_no_ethernet

axi_cdc_dst #(
.LogDepth ( LogDepth ),
.SyncStages ( SyncStages ),
.aw_chan_t ( carfield_axi_slv_aw_chan_t ),
.w_chan_t ( carfield_axi_slv_w_chan_t ),
.b_chan_t ( carfield_axi_slv_b_chan_t ),
.ar_chan_t ( carfield_axi_slv_ar_chan_t ),
.r_chan_t ( carfield_axi_slv_r_chan_t ),
.axi_req_t ( carfield_axi_slv_req_t ),
.axi_resp_t ( carfield_axi_slv_rsp_t )
) i_ethernet_cdc_dst (
.async_data_slave_aw_data_i ( axi_slv_ext_aw_data [EthernetSlvIdx] ),
.async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [EthernetSlvIdx] ),
.async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [EthernetSlvIdx] ),
.async_data_slave_w_data_i ( axi_slv_ext_w_data [EthernetSlvIdx] ),
.async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [EthernetSlvIdx] ),
.async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [EthernetSlvIdx] ),
.async_data_slave_b_data_o ( axi_slv_ext_b_data [EthernetSlvIdx] ),
.async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [EthernetSlvIdx] ),
.async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [EthernetSlvIdx] ),
.async_data_slave_ar_data_i ( axi_slv_ext_ar_data [EthernetSlvIdx] ),
.async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [EthernetSlvIdx] ),
.async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [EthernetSlvIdx] ),
.async_data_slave_r_data_o ( axi_slv_ext_r_data [EthernetSlvIdx] ),
.async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [EthernetSlvIdx] ),
.async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [EthernetSlvIdx] ),
.dst_clk_i ( periph_clk ),
.dst_rst_ni ( periph_rst_n ),
.dst_req_o ( axi_ethernet_req ),
.dst_resp_i ( axi_ethernet_rsp )
);

axi_err_slv #(
.AxiIdWidth ( AxiSlvIdWidth ),
.axi_req_t ( carfield_axi_slv_req_t ),
.axi_resp_t ( carfield_axi_slv_rsp_t ),
.Resp ( axi_pkg::RESP_DECERR ),
.ATOPs ( 1'b0 ),
.MaxTrans ( 4 )
) i_axi_err_slv_ethernet (
.clk_i ( periph_clk ),
.rst_ni ( periph_pwr_on_rst_n ),
.test_i ( test_mode_i ),
// slave port
.slv_req_i ( axi_ethernet_req ),
.slv_resp_o ( axi_ethernet_rsp )
);

assign car_eth_intr = '0;
assign eth_md_o = '0;
assign eth_md_oe = '0;
Expand All @@ -2280,6 +2232,7 @@ end else begin : gen_no_ethernet
assign eth_txck_o = '0;
assign eth_txctl_o = '0;
assign eth_txd_o = '0;

end

// APB peripherals
Expand Down Expand Up @@ -2661,7 +2614,7 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care...
// CAN bus
logic [63:0] can_timestamp;
assign can_timestamp = '1;
if (carfield_pkg::IslandsCfgDefault.EnCan) begin : gen_can
if (carfield_configuration::CanEnable) begin : gen_can
can_top_apb #(
.rx_buffer_size ( 32 ),
.txt_buffer_count ( 2 ),
Expand Down
22 changes: 10 additions & 12 deletions hw/carfield_cfg_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
package carfield_cfg_pkg;

import cheshire_pkg::*;
import carfield_configuration::*;

typedef struct packed {
bit enable;
Expand Down Expand Up @@ -199,19 +200,16 @@ function automatic int unsigned gen_carfield_domains(islands_cfg_t island_cfg);
return ret;
endfunction

// All fields below are in the form: '{enable, base address, address size}.
// The Secure Domain can only be a master of the crossbar. For this reason
// we can only enable it, and provide fake address ranges.
localparam islands_cfg_t CarfieldIslandsCfg = '{
l2_port0: '{1, 'h78000000, 'h00200000},
l2_port1: '{1, 'h78200000, 'h00200000},
safed: '{1, 'h60000000, 'h00800000},
ethernet: '{1, 'h20000000, 'h00001000},
periph: '{1, 'h20001000, 'h00009000},
spatz: '{1, 'h51000000, 'h00800000},
pulp: '{1, 'h50000000, 'h00800000},
secured: '{1, '0, '0 },
mbox: '{1, 'h40000000, 'h00001000}
l2_port0: '{L2Port0Enable, L2Port0Base, L2Port0Size},
l2_port1: '{L2Port1Enable, L2Port1Base, L2Port1Size},
safed: '{SafetyIslandEnable, SafetyIslandBase, SafetyIslandSize},
ethernet: '{EthernetEnable, EthernetBase, EthernetSize},
periph: '{PeriphEnable, PeriphBase, PeriphSize},
spatz: '{SpatzClusterEnable, SpatzClusterBase, SpatzClusterSize},
pulp: '{PulpClusterEnable, PulpClusterBase, PulpClusterSize},
secured: '{SecurityIslandEnable, SecurityIslandBase, SecurityIslandSize},
mbox: '{MailboxEnable, MailboxBase, MailboxSize}
};

// TODO: specify this is for AXI
Expand Down
21 changes: 0 additions & 21 deletions hw/carfield_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -401,27 +401,6 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{
};
// verilog_lint: waive-stop line-length

// Control which island to add
typedef struct packed {
bit EnPulpCluster;
bit EnSafetyIsland;
bit EnSpatzCluster;
bit EnOpenTitan;
bit EnCan;
bit EnEthernet;
} islands_fpga_cfg_t;

// Enable all islands by default
localparam islands_fpga_cfg_t IslandsCfgDefault = '{
EnPulpCluster : 1,
EnSafetyIsland : 1,
EnSpatzCluster : 1,
EnOpenTitan : 1,
EnCan : 1,
EnEthernet : 0,
default : '1
};

// CDC FIFO parameters (FIFO depth).
localparam int unsigned LogDepth = 3;

Expand Down
50 changes: 50 additions & 0 deletions hw/configs/carfield_default_cfg.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,50 @@
// Copyright 2022 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
//
// Yvan Tortorella <[email protected]>

package carfield_configuration;

import cheshire_pkg::*;

//L2, port 0
localparam bit L2Port0Enable = 1;
localparam doub_bt L2Port0Base = 'h78000000;
localparam doub_bt L2Port0Size = 'h00200000;
// L2, port 1
localparam bit L2Port1Enable = 1;
localparam doub_bt L2Port1Base = L2Port0Base;
localparam doub_bt L2Port1Size = L2Port0Size;
// Safety Island
localparam bit SafetyIslandEnable = 1;
localparam doub_bt SafetyIslandBase = 'h60000000;
localparam doub_bt SafetyIslandSize = 'h00800000;
// Ethernet
localparam bit EthernetEnable = 0;
localparam doub_bt EthernetBase = 'h20000000;
localparam doub_bt EthernetSize = 'h00001000;
// Peripherals
localparam bit PeriphEnable = 1;
localparam doub_bt PeriphBase = 'h20001000;
localparam doub_bt PeriphSize = 'h00009000;
// Spatz cluster
localparam bit SpatzClusterEnable = 1;
localparam doub_bt SpatzClusterBase = 'h51000000;
localparam doub_bt SpatzClusterSize = 'h00800000;
// PULP cluster
localparam bit PulpClusterEnable = 1;
localparam doub_bt PulpClusterBase = 'h50000000;
localparam doub_bt PulpClusterSize = 'h00800000;
// Security Island
localparam bit SecurityIslandEnable = 1;
localparam doub_bt SecurityIslandBase = 'h0;
localparam doub_bt SecurityIslandSize = 'h0;
// Mailbox
localparam bit MailboxEnable = 1;
localparam doub_bt MailboxBase = 'h40000000;
localparam doub_bt MailboxSize = 'h00001000;
// Can
localparam bit CanEnable = 1;

endpackage
63 changes: 63 additions & 0 deletions hw/configs/carfield_fpga_cfg.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,63 @@
// Copyright 2022 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
//
// Yvan Tortorella <[email protected]>

package carfield_configuration;

import cheshire_pkg::*;

`ifndef GEN_PULP_CLUSTER
`define GEN_PULP_CLUSTER 0
`endif
`ifndef GEN_SAFETY_ISLAND
`define GEN_SAFETY_ISLAND 0
`endif
`ifndef GEN_SPATZ_CLUSTER
`define GEN_SPATZ_CLUSTER 0
`endif
`ifndef GEN_OPEN_TITAN
`define GEN_OPEN_TITAN 0
`endif

//L2, port 0
localparam bit L2Port0Enable = 1;
localparam doub_bt L2Port0Base = 'h78000000;
localparam doub_bt L2Port0Size = 'h00200000;
// L2, port 1
localparam bit L2Port1Enable = 1;
localparam doub_bt L2Port1Base = L2Port0Base;
localparam doub_bt L2Port1Size = L2Port0Size;
// Safety Island
localparam bit SafetyIslandEnable = `GEN_SAFETY_ISLAND;
localparam doub_bt SafetyIslandBase = 'h60000000;
localparam doub_bt SafetyIslandSize = 'h00800000;
// Ethernet
localparam bit EthernetEnable = 0;
localparam doub_bt EthernetBase = 'h20000000;
localparam doub_bt EthernetSize = 'h00001000;
// Peripherals
localparam bit PeriphEnable = 1;
localparam doub_bt PeriphBase = 'h20001000;
localparam doub_bt PeriphSize = 'h00009000;
// Spatz cluster
localparam bit SpatzClusterEnable = `GEN_SPATZ_CLUSTER;
localparam doub_bt SpatzClusterBase = 'h51000000;
localparam doub_bt SpatzClusterSize = 'h00800000;
// PULP cluster
localparam bit PulpClusterEnable = `GEN_PULP_CLUSTER;
localparam doub_bt PulpClusterBase = 'h50000000;
localparam doub_bt PulpClusterSize = 'h00800000;
// Security Island
localparam bit SecurityIslandEnable = `GEN_OPEN_TITAN;
localparam doub_bt SecurityIslandBase = 'h0;
localparam doub_bt SecurityIslandSize = 'h0;
// Mailbox
localparam bit MailboxEnable = 1;
localparam doub_bt MailboxBase = 'h40000000;
localparam doub_bt MailboxSize = 'h00001000;
// Can
localparam bit CanEnable = 0;

endpackage
24 changes: 0 additions & 24 deletions target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv
Original file line number Diff line number Diff line change
Expand Up @@ -399,32 +399,9 @@ module carfield_top_xilinx
// Carfield Cfg //
//////////////////

`ifndef GEN_PULP_CLUSTER
`define GEN_PULP_CLUSTER 0
`endif
`ifndef GEN_SAFETY_ISLAND
`define GEN_SAFETY_ISLAND 0
`endif
`ifndef GEN_SPATZ_CLUSTER
`define GEN_SPATZ_CLUSTER 0
`endif
`ifndef GEN_OPEN_TITAN
`define GEN_OPEN_TITAN 0
`endif

localparam cheshire_cfg_t Cfg = carfield_pkg::CarfieldCfgDefault;
`CHESHIRE_TYPEDEF_ALL(carfield_, Cfg)

localparam islands_cfg_t IslandsCfg = '{
EnPulpCluster : `GEN_PULP_CLUSTER,
EnSafetyIsland : `GEN_SAFETY_ISLAND,
EnSpatzCluster : `GEN_SPATZ_CLUSTER,
EnOpenTitan : `GEN_OPEN_TITAN,
EnCan : 0,
EnEthernet : 0,
default : '1
};

///////////////////
// LLC interface //
///////////////////
Expand Down Expand Up @@ -498,7 +475,6 @@ module carfield_top_xilinx

carfield #(
.Cfg (carfield_pkg::CarfieldCfgDefault),
.IslandsCfg(IslandsCfg),
.reg_req_t(carfield_reg_req_t),
.reg_rsp_t(carfield_reg_rsp_t),
`ifdef GEN_NO_HYPERBUS
Expand Down

0 comments on commit afe2df1

Please sign in to comment.