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@@ -650,6 +650,19 @@ <h3 id="memory-requirements-for-physical-implementation">Memory requirements for
 <p>Given Carfield's complexity and heterogeneity, in the following we provide an overview of Carfield's
 on-chip memory requirements to help ASIC developers who wants to implement Carfield or integrate it
 into larger platforms.</p>
+<p>Carfield makes large use of scratchpad memories (SPM), implemented as SRAMs and explicitely managed
+in SW. To help the reader, we consider an SPM as described by the following parameters:</p>
+<ul>
+<li><code>NumWords</code>: The number of words. Assuming the SPM as a matrix, it corresponds to the number of
+  rows. Assuming the <em>domain</em>'s memory system has address width <code>AddrWidth</code>, then <code>NumWords =
+  2**(AddrWidth)</code>, i.e. <code>2**AddrWidth</code> data words can be addressed.</li>
+<li><code>DataWidth</code>: The data width of a <em>word</em> in the <em>domain</em>'s memory system. Typically, it is 32-bit
+  or 64-bit. If ECC is implemented, it is larger to account for the extra bits.</li>
+<li><code>NumBanks</code>: number of banks of size <code>(NumWords*DataWidth)/8</code> B.</li>
+</ul>
+<p>The total size is computed as</p>
+<pre><code>Total size [B] = (NumWords * DataWidth [bit] * NumBanks)/8 [B]
+</code></pre>
 <p>TODO</p>