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<ul class="md-nav__list">

<li class="md-nav__item">
<a href="#computing-domain" class="md-nav__link">
<span class="md-ellipsis">
Computing Domain
</span>
</a>

<nav class="md-nav" aria-label="Computing Domain">
<ul class="md-nav__list">

<li class="md-nav__item">
<a href="#host-domain-cheshire" class="md-nav__link">
<span class="md-ellipsis">
Host domain (Cheshire)
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</li>

</ul>
</nav>

</li>

<li class="md-nav__item">
<a href="#memory-domain" class="md-nav__link">
<span class="md-ellipsis">
Memory Domain
</span>
</a>

<nav class="md-nav" aria-label="Memory Domain">
<ul class="md-nav__list">

<li class="md-nav__item">
<a href="#dynamic-scratchpad-memory-spm" class="md-nav__link">
<span class="md-ellipsis">
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</li>

<li class="md-nav__item">
<a href="#external-dram" class="md-nav__link">
<a href="#partitionable-hybrid-llcspm" class="md-nav__link">
<span class="md-ellipsis">
External DRAM
Partitionable hybrid LLC/SPM
</span>
</a>

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</ul>
</nav>

</li>

</ul>
</nav>

</li>

<li class="md-nav__item">
<a href="#interconnect" class="md-nav__link">
<a href="#system-bus-interconnect" class="md-nav__link">
<span class="md-ellipsis">
Interconnect
System bus interconnect
</span>
</a>

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</li>

<li class="md-nav__item">
<a href="#peripheral-domain" class="md-nav__link">
<a href="#hyperbus-off-chip-link" class="md-nav__link">
<span class="md-ellipsis">
HyperBus off-chip link
</span>
</a>

</li>

<li class="md-nav__item">
<a href="#peripherals" class="md-nav__link">
<span class="md-ellipsis">
Peripheral Domain
Peripherals
</span>
</a>

<nav class="md-nav" aria-label="Peripheral Domain">
<nav class="md-nav" aria-label="Peripherals">
<ul class="md-nav__list">

<li class="md-nav__item">
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<ul class="md-nav__list">

<li class="md-nav__item">
<a href="#computing-domain" class="md-nav__link">
<span class="md-ellipsis">
Computing Domain
</span>
</a>

<nav class="md-nav" aria-label="Computing Domain">
<ul class="md-nav__list">

<li class="md-nav__item">
<a href="#host-domain-cheshire" class="md-nav__link">
<span class="md-ellipsis">
Host domain (Cheshire)
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</li>

</ul>
</nav>

</li>

<li class="md-nav__item">
<a href="#memory-domain" class="md-nav__link">
<span class="md-ellipsis">
Memory Domain
</span>
</a>

<nav class="md-nav" aria-label="Memory Domain">
<ul class="md-nav__list">

<li class="md-nav__item">
<a href="#dynamic-scratchpad-memory-spm" class="md-nav__link">
<span class="md-ellipsis">
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</li>

<li class="md-nav__item">
<a href="#external-dram" class="md-nav__link">
<a href="#partitionable-hybrid-llcspm" class="md-nav__link">
<span class="md-ellipsis">
External DRAM
Partitionable hybrid LLC/SPM
</span>
</a>

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</ul>
</nav>

</li>

</ul>
</nav>

</li>

<li class="md-nav__item">
<a href="#interconnect" class="md-nav__link">
<a href="#system-bus-interconnect" class="md-nav__link">
<span class="md-ellipsis">
Interconnect
System bus interconnect
</span>
</a>

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</li>

<li class="md-nav__item">
<a href="#peripheral-domain" class="md-nav__link">
<a href="#hyperbus-off-chip-link" class="md-nav__link">
<span class="md-ellipsis">
Peripheral Domain
HyperBus off-chip link
</span>
</a>

<nav class="md-nav" aria-label="Peripheral Domain">
</li>

<li class="md-nav__item">
<a href="#peripherals" class="md-nav__link">
<span class="md-ellipsis">
Peripherals
</span>
</a>

<nav class="md-nav" aria-label="Peripherals">
<ul class="md-nav__list">

<li class="md-nav__item">
Expand Down Expand Up @@ -1154,7 +1112,7 @@ <h1 id="architecture">Architecture</h1>
<p>The above block diagram depicts a fully-featured Carfield SoC, which currently provides:</p>
<ul>
<li>
<p><strong>Computing Domain</strong>:</p>
<p><strong>Domains</strong>:</p>
<ul>
<li><em>Host domain</em> (Cheshire), a Linux-capable RV64 system based on dual-core CVA6 processors with
self-invalidation coherency mechanism</li>
Expand All @@ -1170,15 +1128,16 @@ <h1 id="architecture">Architecture</h1>
</ul>
</li>
<li>
<p><strong>Memory Domain</strong>:</p>
<p><strong>On-chip and off-chip memory endpoints</strong>:</p>
<ul>
<li><em>Dynamic SPM</em>: dynamically configurable scratchpad memory (SPM) for <em>interleaved</em> or
<em>contiguous</em> accesses aiming at reducing systematic bus conflicts to improve the
time-predictability of the on-chip communication</li>
<li><em>LLC SPM</em>: the last-level cache (<em>host domain</em>) can be configured as SPM at runtime, as
described in Cheshire's <a href="https://pulp-platform.github.io/cheshire/um/arch/">Architecture</a></li>
<li><em>Partitionable hybrid LLC SPM</em>: the last-level cache (<em>host domain</em>) can be configured as SPM
at runtime, as described in Cheshire's
<a href="https://pulp-platform.github.io/cheshire/um/arch/">Architecture</a></li>
<li><em>External DRAM</em>: off-chip HyperRAM (Infineon) interfaced with in-house, open-source AXI4
Hyberbus memory controller and digital PHY</li>
Hyberbus memory controller and digital PHY connected to Cheshire's LLC</li>
</ul>
</li>
<li>
Expand Down Expand Up @@ -2763,20 +2722,14 @@ <h2 id="interrupt-map">Interrupt map</h2>
</tbody>
</table>
<h2 id="domains">Domains</h2>
<p>We divide Carfield domains in two macro groups, the <a href="#computing-domains">Computing Domain</a> and the
<a href="#memory-domain">Memory Domain</a>. They are both fragmented into smaller domains, described in the
following two sections.</p>
<p>The total number of domains is 7 (<strong>computing</strong>: <em>host domain</em>, <em>safe domain</em>, <em>secure domain</em>,
<em>integer PMCA domain</em>, <em>vectorial PMCA domain</em>, <em>peripheral domain</em>, <strong>memory</strong>: <em>dynamic SPM
domain</em>).</p>
<hr />
<p><strong>Note for the reader</strong></p>
<p>Carfield's domains live in dedicated repositories. We invite the reader to consult the documentation
of each domain for more information. Below, we focus on their parameterization within Carfield.</p>
<p>For more information about memory requirements, visit <a href="../../tg/synth/">Synthesis and physical
<p>The total number of domains is 7: <em>host domain</em>, <em>safe domain</em>, <em>secure domain</em>, <em>integer PMCA
domain</em>, <em>vectorial PMCA domain</em>, <em>peripheral domain</em>, <em>dynamic SPM</em>.</p>
<p>Carfield's domains live in dedicated repositories. We therefore invite the reader to consult the
documentation of each domain.</p>
<p>For more information about domains' memory requirements, visit <a href="../../tg/synth/">Synthesis and physical
implementation</a>.</p>
<h3 id="computing-domain">Computing Domain</h3>
<h4 id="host-domain-cheshire"><a href="https://github.com/pulp-platform/cheshire">Host domain (Cheshire)</a></h4>
<p>Below, we focus on domains' parameterization within Carfield.</p>
<h3 id="host-domain-cheshire"><a href="https://github.com/pulp-platform/cheshire">Host domain (Cheshire)</a></h3>
<p>The <em>host domain</em> (Cheshire) embeds all the necessary components required to run OSs such as
embedded Linux. It has two orthogonal <em>operation modes</em>.</p>
<ol>
Expand Down Expand Up @@ -2838,7 +2791,7 @@ <h4 id="host-domain-cheshire"><a href="https://github.com/pulp-platform/cheshire
<li>All Cheshire peripherals, except for VGA</li>
</ul>
<p>By default, Cheshire hosts 128KiB of hybrid LLC/SPM, user-configurable.</p>
<h4 id="safe-domain"><a href="https://github.com/pulp-platform/safety_island">Safe domain</a></h4>
<h3 id="safe-domain"><a href="https://github.com/pulp-platform/safety_island">Safe domain</a></h3>
<p>The <em>safe domain</em> is a simple MCU-like domain that comprises three 32-bit real-time CV32E40P
(CV32RT) RISC-V cores operating in triple-core-lockstep mode (TCLS).</p>
<p>These cores, enhanced with the RISC-V CLIC controller and optimized for fast interrupt handling and
Expand All @@ -2862,7 +2815,7 @@ <h4 id="safe-domain"><a href="https://github.com/pulp-platform/safety_island">Sa
</ul>
<p>By default, the processing elements share access to 128KiB of SPM for instructions and data,
user-configurable.</p>
<h4 id="secure-domain"><a href="https://github.com/pulp-platform/opentitan/tree/carfield-soc">Secure domain</a></h4>
<h3 id="secure-domain"><a href="https://github.com/pulp-platform/opentitan/tree/carfield-soc">Secure domain</a></h3>
<p>The secure domain, based on the <a href="https://opentitan.org/book/doc/introduction.html">OpenTitan
project</a>, serves as the Hardware Root-of-Trust
(HWRoT) of the platform. It handles <em>secure boot</em> and system integrity monitoring fully in HW
Expand All @@ -2888,10 +2841,10 @@ <h4 id="secure-domain"><a href="https://github.com/pulp-platform/opentitan/tree/
</li>
</ul>
<p>By default, the secure domain hosts 512KiB of main SPM, and 16KiB of OTP memory, user-configurable.</p>
<h4 id="accelerator-domain">Accelerator domain</h4>
<h3 id="accelerator-domain">Accelerator domain</h3>
<p>To augment computational capabilities, Carfield incorporates two PMCAs, described below. Both PMCAs
integrate DMA engines to independently fetch data from the on-chip SPM or external DRAM.</p>
<h5 id="hmr-integer-pmca"><a href="https://github.com/pulp-platform/pulp_cluster/tree/yt/rapidrecovery">HMR integer PMCA</a></h5>
<h4 id="hmr-integer-pmca"><a href="https://github.com/pulp-platform/pulp_cluster/tree/yt/rapidrecovery">HMR integer PMCA</a></h4>
<p>The <a href="https://arxiv.org/abs/2303.08706">hybrid modular redundancy (HMR) <em>integer PMCA</em></a> is
specialized in accelerating the inference of Deep Learning and Machine Learning models. The
multicore accelerator is built around 12 32-bit RISC-V cores empowered with ISA extensions, enabling
Expand All @@ -2918,7 +2871,7 @@ <h5 id="hmr-integer-pmca"><a href="https://github.com/pulp-platform/pulp_cluster
provides the highest fault resilience in this configuration, at the cost of reduced performance.</p>
<p>By default, the integer PMCA's processing elements and tensor accelerator share access to 256KiB of
L1 SPM, user-configurable.</p>
<h5 id="vectorial-pmca"><a href="https://github.com/pulp-platform/spatz">Vectorial PMCA</a></h5>
<h4 id="vectorial-pmca"><a href="https://github.com/pulp-platform/spatz">Vectorial PMCA</a></h4>
<p>The <a href="https://dl.acm.org/doi/abs/10.1145/3508352.3549367"><em>vectorial PMCA</em>, or Spatz PMCA</a> handles
vectorizable multi-format floating-point workloads.</p>
<p>A Spatz vector unit acts as a coprocessor of the <a href="https://github.com/pulp-platform/snitch_cluster">Snitch
Expand All @@ -2934,8 +2887,7 @@ <h5 id="vectorial-pmca"><a href="https://github.com/pulp-platform/spatz">Vectori
<p>Each FPU supports <em>FP8</em>, <em>FP16</em>, <em>FP32</em>, and <em>FP64</em> computation, while the IPU supports 8, 16, 32,
and 64-bit integer computation.</p>
<p>By default, the CCs share access to 128KiB of L1 SPM, user-configurable.</p>
<h3 id="memory-domain">Memory Domain</h3>
<h4 id="dynamic-scratchpad-memory-spm"><a href="https://github.com/pulp-platform/dyn_spm">Dynamic scratchpad memory (SPM)</a></h4>
<h3 id="dynamic-scratchpad-memory-spm"><a href="https://github.com/pulp-platform/dyn_spm">Dynamic scratchpad memory (SPM)</a></h3>
<p>The dynamic SPM features dynamically switching address mapping policy. It manages the following
features:</p>
<ul>
Expand All @@ -2947,20 +2899,12 @@ <h4 id="dynamic-scratchpad-memory-spm"><a href="https://github.com/pulp-platform
<li>ECC-equipped memory banks</li>
</ul>
<p>By default, Carfield hosts 1MiB of dynamic SPM, user-configurable.</p>
<h4 id="external-dram">External DRAM</h4>
<p>Carfield integrates a in-house, open-source implementation of Infineon' <a href="https://github.com/pulp-platform/hyperbus">HyperBus off-chip
link</a> to connect to external HyperRAM modules.</p>
<p>Despite describing it as part of the Memory Domain, the HyperBus is logically part of the
<em>peripheral domain</em>.</p>
<p>It manages the following features:</p>
<ul>
<li>An AXI interface; in Carfield, it attaches to Cheshire's LLC</li>
<li>A configurable number of physical HyperRAM chips it can be attached to; by default, support for 2
physical chips is provided</li>
<li>Support for HyperRAM chips with different densities (from 8MiB to 64MiB per chip aligned with
specs).</li>
</ul>
<h2 id="interconnect">Interconnect</h2>
<h3 id="partitionable-hybrid-llcspm"><a href="https://github.com/pulp-platform/axi_llc">Partitionable hybrid LLC/SPM</a></h3>
<p>Carfield hosts a LLC optionaly reconfigurable as SPM during runtime. In addition, the LLC supports
HW-based partitioning to exploit intra-process or inter-processes isolation, improving the system's
predictability. The LLC is described in detail in Cheshire's
<a href="https://pulp-platform.github.io/cheshire/um/arch">Architecture</a>.</p>
<h2 id="system-bus-interconnect">System bus interconnect</h2>
<p>The interconnect is composed of a main <a href="https://github.com/pulp-platform/axi">AXI4</a> matrix (or
crossbar) with AXI5 atomic operations (ATOPs) support. The crossbar extends Cheshire's with
additional external AXI manager and subordinate ports.</p>
Expand Down Expand Up @@ -3454,7 +3398,19 @@ <h2 id="platform-control-registers">Platform control registers</h2>
</tr>
</tbody>
</table>
<h2 id="peripheral-domain">Peripheral Domain</h2>
<h2 id="hyperbus-off-chip-link">HyperBus off-chip link</h2>
<p>Carfield integrates a in-house, open-source implementation of Infineon' <a href="https://github.com/pulp-platform/hyperbus">HyperBus off-chip
controller</a> to connect to external HyperRAM modules.</p>
<p>It manages the following features:</p>
<ul>
<li>An AXI interface that attaches to Cheshire's <a href="#partitionable-hybrid-llc-spm">partitionable hybrid
LLC/SPM</a></li>
<li>A configurable number of physical HyperRAM chips it can be attached to; by default, support for 2
physical chips is provided</li>
<li>Support for HyperRAM chips with different densities (from 8MiB to 64MiB per chip aligned with
specs).</li>
</ul>
<h2 id="peripherals">Peripherals</h2>
<p>Carfield enhances Cheshire's peripheral subsystem with additional capabilities.</p>
<p>An external AXI manager port is attached to the matrix crossbar. The 64-bit data, 48-bit address AXI
protocol is converted to the slower, 32-bit data and address APB protocol. An APB demultiplexer
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