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Fix configuration without ECC #17

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Fix configuration without ECC #17

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c7b27b2
Fix configuration without ECC
ricted98 Aug 22, 2024
f83be3f
Fix bug: when ECC off, the LLC would get stuck at BIST.
Aquaticfuller Aug 22, 2024
2f23e6f
Fix signal naming
ricted98 Aug 22, 2024
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39 changes: 18 additions & 21 deletions src/axi_llc_reg_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -302,25 +302,6 @@ module axi_llc_reg_wrap #(
.in_select_i ( ~llc_reg_req_en )
);


// Generated 32-bit RegBus register file
axi_llc_reg_top #(
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_resp_t )
) i_llc_config_regfile (
.clk_i,
.rst_ni,
.reg_req_i ( llc_reg_req [0] ),
.reg_rsp_o ( llc_reg_resp [0] ),

// To HW
.reg2hw ( config_reg2hw ), // Write
.hw2reg ( config_hw2reg ), // Read

// Config
.devmode_i ( 1'b0 ) // If 1, explicit error return for unmapped register access
);

// ECC manager signals
logic [EccSignalWidth-1:0] bank_faults_flat;
logic [EccSignalWidth-1:0] scrubber_fix_flat;
Expand Down Expand Up @@ -360,11 +341,27 @@ module axi_llc_reg_wrap #(
end else begin: gen_no_ecc_connection
assign llc_reg_req[0] = conf_req_i;
assign conf_resp_o = llc_reg_resp[0];
assign tag_ecc_info = '0;
assign data_ecc_info = '0;
assign scrub_trigger = '0;
end

// Generated 32-bit RegBus register file
axi_llc_reg_top #(
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_resp_t )
) i_llc_config_regfile (
.clk_i,
.rst_ni,
.reg_req_i ( llc_reg_req [0] ),
.reg_rsp_o ( llc_reg_resp [0] ),

// To HW
.reg2hw ( config_reg2hw ), // Write
.hw2reg ( config_hw2reg ), // Read

// Config
.devmode_i ( 1'b0 ) // If 1, explicit error return for unmapped register access
);

// Registerfile agnostic axi_llc toplevel - configured for 64-bit internal registers
axi_llc_top #(
.SetAssociativity ( SetAssociativity ),
Expand Down
24 changes: 12 additions & 12 deletions src/axi_llc_sram.sv
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Expand Up @@ -157,7 +157,7 @@ module axi_llc_sram #(

end else begin: gen_standard_sram
assign gnt_o = 1'b1;
data_t rdata_cmp, rdata_cmp_q;
data_t rdata_cut, rdata_cut_q;
tc_sram #(
.NumWords ( NumWords ),
.DataWidth ( DataWidth ),
Expand All @@ -174,26 +174,26 @@ module axi_llc_sram #(
.addr_i ( addr_i ),
.wdata_i ( wdata_i ),
.be_i ( be_i ),
// .rdata_o ( rdata_o )
.rdata_o ( rdata_cmp )
.rdata_o ( rdata_cut )
);

shift_reg #(
.dtype(data_t),
.Depth(NumOutputCuts)
) i_rdata_cmp_q (
.clk_i,
.rst_ni,
.d_i (rdata_cmp),
.d_o (rdata_cmp_q)
);
.dtype(data_t),
.Depth(NumOutputCuts)
) i_rdata_cut_q (
.clk_i,
.rst_ni,
.d_i (rdata_cut),
.d_o (rdata_cut_q)
);

assign rdata_o = rdata_cut_q;

// // Assertions
// // pragma translate_off
// `ifndef VERILATOR
// data_cmp: assert property ( @(posedge clk_i) disable iff (!rst_ni)
// (hsk_d & ~we_i) ##(NumOutputCuts+1) 1 |-> (rdata_o == rdata_cmp_q)) else
// (hsk_d & ~we_i) ##(NumOutputCuts+1) 1 |-> (rdata_o == rdata_cut_q)) else
// $info(1, "[data_cmp] data mismatch");
// `endif
// // pragma translate_on
Expand Down
2 changes: 1 addition & 1 deletion src/hit_miss_detect/axi_llc_tag_store.sv
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Expand Up @@ -441,7 +441,7 @@ module axi_llc_tag_store #(

assign ram_rdata_en [i] = ram_rdata_q_valid_set[i] & ~ram_rdata_q_valid_clr[i] & ~ram_rdata_q_valid[i];
assign ram_rdata_q_valid_en [i] = ram_rdata_q_valid_set[i] | ram_rdata_q_valid_clr [i];
assign ram_rdata_q_valid_set[i] = ~ram_rdata_q_valid[i] & ((|ram_rvalid) | (ram_rvalid_q));
assign ram_rdata_q_valid_set[i] = ~ram_rdata_q_valid[i] & ((|ram_rvalid) | (ram_rvalid_q)) & ~bist_valid;
assign ram_rdata_q_valid_clr[i] = (res_valid && res_ready);
assign ram_rdata_q_valid_nxt[i] = ram_rdata_q_valid_set[i] & ~ram_rdata_q_valid_clr[i];

Expand Down