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    313 repositories

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •30•107•6•4•Updated Aug 21, 2025Aug 21, 2025

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      SystemVerilog
      •
      Apache License 2.0
      •3•4•2•3•Updated Aug 21, 2025Aug 21, 2025

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •35•174•9•3•Updated Aug 21, 2025Aug 21, 2025

    • datamover

      Public
      C
      •
      Other
      •0•1•0•2•Updated Aug 21, 2025Aug 21, 2025

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •36•48•7•4•Updated Aug 21, 2025Aug 21, 2025

    • pulp-trainlib

      Public
      Floating-Point Optimized On-Device Learning Library for the PULP Platform.
      C
      •
      Apache License 2.0
      •17•36•4•2•Updated Aug 21, 2025Aug 21, 2025

    • regression_tests

      Public
      C
      •19•8•3•2•Updated Aug 21, 2025Aug 21, 2025

    • pulp-nnx

      Public
      C
      •
      Apache License 2.0
      •2•8•0•1•Updated Aug 21, 2025Aug 21, 2025

    • hwpe-ctrl

      Public
      IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •19•6•1•4•Updated Aug 21, 2025Aug 21, 2025

    • TeraNoC

      Public
      An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.
      C
      •
      Apache License 2.0
      •0•5•0•0•Updated Aug 20, 2025Aug 20, 2025

    • timer_unit

      Public
      SystemVerilog
      •
      Other
      •4•2•0•0•Updated Aug 20, 2025Aug 20, 2025

    • ManyRVData

      Public
      0•0•0•1•Updated Aug 20, 2025Aug 20, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •25•114•1•2•Updated Aug 20, 2025Aug 20, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •74•278•14•21•Updated Aug 19, 2025Aug 19, 2025

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •22•30•3•6•Updated Aug 19, 2025Aug 19, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •68•131•2•6•Updated Aug 19, 2025Aug 19, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •18•44•8•6•Updated Aug 19, 2025Aug 19, 2025

    • pulp-riscv-gnu-toolchain

      Public
      C
      •
      Other
      •52•90•25•0•Updated Aug 19, 2025Aug 19, 2025

    • pulp-riscv-binutils-gdb

      Public
      C
      •
      Other
      •21•0•2•4•Updated Aug 19, 2025Aug 19, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •83•99•21•8•Updated Aug 19, 2025Aug 19, 2025

    • picobello

      Public
      whatever it means
      C
      •
      Other
      •6•9•7•3•Updated Aug 19, 2025Aug 19, 2025

    • pulp-riscv-gcc

      Public
      C
      •
      Other
      •18•7•1•1•Updated Aug 19, 2025Aug 19, 2025

    • CHERI-Litmus

      Public
      A tool to run litmus tests on bare-metal hardware
      C
      •
      Other
      •13•3•0•1•Updated Aug 19, 2025Aug 19, 2025

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •174•648•33•12•Updated Aug 18, 2025Aug 18, 2025

    • pulp-sdk

      Public
      C
      •
      Apache License 2.0
      •78•115•17•9•Updated Aug 17, 2025Aug 17, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •824•21•1•7•Updated Aug 16, 2025Aug 16, 2025

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •6•18•1•6•Updated Aug 15, 2025Aug 15, 2025

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •305•1.4k•46•19•Updated Aug 15, 2025Aug 15, 2025

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •15•14•5•4•Updated Aug 14, 2025Aug 14, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •54•302•3•5•Updated Aug 14, 2025Aug 14, 2025