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    298 repositories

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •53•225•9•17•Updated Feb 23, 2025Feb 23, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •724•17•0•6•Updated Feb 22, 2025Feb 22, 2025

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •135•399•67•6•Updated Feb 22, 2025Feb 22, 2025

    • llvm-project

      Public
      13k•7•7•1•Updated Feb 21, 2025Feb 21, 2025

    • redmule

      Public
      SystemVerilog
      •
      Other
      •13•42•1•3•Updated Feb 21, 2025Feb 21, 2025

    • chimera

      Public
      Python
      •
      Other
      •3•14•9•3•Updated Feb 21, 2025Feb 21, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •19•91•1•2•Updated Feb 21, 2025Feb 21, 2025

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •15•6•0•6•Updated Feb 21, 2025Feb 21, 2025

    • quadrilatero

      Public
      matrix-coprocessor for RISC-V
      C
      •
      Other
      •2•11•0•0•Updated Feb 21, 2025Feb 21, 2025

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •11•12•3•5•Updated Feb 21, 2025Feb 21, 2025

    • hwpe-ctrl

      Public
      IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •17•6•3•4•Updated Feb 21, 2025Feb 21, 2025

    • pulp-nnx

      Public
      C
      •
      Apache License 2.0
      •0•4•0•0•Updated Feb 21, 2025Feb 21, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •8•53•1•0•Updated Feb 20, 2025Feb 20, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •22•71•4•6•Updated Feb 20, 2025Feb 20, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •47•284•3•4•Updated Feb 20, 2025Feb 20, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •59•67•16•6•Updated Feb 20, 2025Feb 20, 2025

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •36•40•7•4•Updated Feb 20, 2025Feb 20, 2025

    • picobello

      Public
      whatever it means
      SystemVerilog
      •
      Other
      •0•3•7•0•Updated Feb 20, 2025Feb 20, 2025

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •29•120•7•6•Updated Feb 19, 2025Feb 19, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •11•26•7•5•Updated Feb 17, 2025Feb 17, 2025

    • regression_tests

      Public
      C
      •17•8•3•1•Updated Feb 16, 2025Feb 16, 2025

    • dory

      Public
      A tool to deploy Deep Neural Networks on PULP-based SoC's
      Python
      •
      Apache License 2.0
      •22•79•1•4•Updated Feb 14, 2025Feb 14, 2025

    • flex-v

      Public
      Core used inside the PULP cluster with mixed-precision MAC&LOAD (formerly RI5CY, now Flex-V)
      SystemVerilog
      •
      Other
      •0•1•0•0•Updated Feb 14, 2025Feb 14, 2025

    • cluster_icache

      Public
      An instruction cache for processor clusters, originally developed for the snitch cluster.
      SystemVerilog
      •
      Other
      •2•2•0•5•Updated Feb 14, 2025Feb 14, 2025

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •29•172•14•5•Updated Feb 12, 2025Feb 12, 2025

    • u-boot

      Public
      Unofficial development fork of U-Boot
      C
      •12•0•0•1•Updated Feb 10, 2025Feb 10, 2025

    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      •
      Other
      •540•0•0•2•Updated Feb 10, 2025Feb 10, 2025

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •68•1•0•2•Updated Feb 10, 2025Feb 10, 2025

    • control-pulp

      Public
      C
      •
      Other
      •2•3•3•2•Updated Feb 8, 2025Feb 8, 2025

    • serial_link

      Public
      A simple, scalable, source-synchronous, all-digital DDR link
      SystemVerilog
      •
      Other
      •10•22•0•0•Updated Feb 8, 2025Feb 8, 2025