bugfixes; set store flag to allow for loads; update encoding

Change-Id: I1d2cfed7d551dbe06cf08a17a9a16ac677f66502
project-starch · Sep 25, 2023 · 93e7865 · 93e7865
1 parent 4fc5197
commit 93e7865
Show file tree

Hide file tree

Showing 2 changed files with 43 additions and 13 deletions.
diff --git a/src/arch/riscvcapstone/isa/decoder.isa b/src/arch/riscvcapstone/isa/decoder.isa
@@ -1628,7 +1628,7 @@ decode QUADRANT default Unknown::unknown() {
                                 static_cast<unsigned int>(rs1_cap.type()),
                                 rs1_cap.nodeId());
                     }}, IsSerializing, IsNonSpeculative, IsSerializeAfter);
-                    0xd: printregs ({{
+                    0x12: printregs ({{
                         using namespace gem5::RiscvcapstoneISA::o3;
                         DynInst *dyn_inst = dynamic_cast<DynInst *>(xc);
                         assert(dyn_inst);
@@ -1660,10 +1660,12 @@ decode QUADRANT default Unknown::unknown() {
                 format ROp {
                     0xc: cssetworld ({{
                         Rs1_ud;
-                        //0xd: csonpartition
                         //0xe: csseteh
                         //0xf: csonnormaleh
                     }});
+                    0xd: csonpartition ({{
+                        Rs1_ud;
+                    }});
                 }
                 format RNodeOp {
                     0x11: printnode ({{
@@ -1688,55 +1690,83 @@ decode QUADRANT default Unknown::unknown() {
                         Rs1_trv;
                         getMemLE(pkt, Mem_sb, traceData);
 
-                        Rd_trv.getRegVal().intVal() = Mem_sb;
+                        ConstTaggedRegVal temp_regval;
+                        temp_regval.setTag(false);
+                        temp_regval.getRegVal().intVal() = Mem_sb;
+
+                        Rd_trv = temp_regval;
                     }});
                 0x1: lh ({{ //ea_code
 
                     }}, {{ //comp_code
                         Rs1_trv;
                         getMemLE(pkt, Mem_sh, traceData);
 
-                        Rd_trv.getRegVal().intVal() = Mem_sh;
+                        ConstTaggedRegVal temp_regval;
+                        temp_regval.setTag(false);
+                        temp_regval.getRegVal().intVal() = Mem_sh;
+
+                        Rd_trv = temp_regval;
                     }});
                 0x2: lw ({{ //ea_code
 
                     }}, {{ //comp_code
                         Rs1_trv;
                         getMemLE(pkt, Mem_sw, traceData);
 
-                        Rd_trv.getRegVal().intVal() = Mem_sw;
+                        ConstTaggedRegVal temp_regval;
+                        temp_regval.setTag(false);
+                        temp_regval.getRegVal().intVal() = Mem_sw;
+
+                        Rd_trv = temp_regval;
                     }});
                 0x3: ld ({{ //ea_code
 
                     }}, {{ //comp_code
                         Rs1_trv;
                         getMemLE(pkt, Mem_sd, traceData);
 
-                        Rd_trv.getRegVal().intVal() = Mem_sd;
+                        ConstTaggedRegVal temp_regval;
+                        temp_regval.setTag(false);
+                        temp_regval.getRegVal().intVal() = Mem_sd;
+
+                        Rd_trv = temp_regval;
                     }});
                 0x4: lbu ({{ //ea_code
 
                     }}, {{ //comp_code
                         Rs1_trv;
                         getMemLE(pkt, Mem_ub, traceData);
 
-                        Rd_trv.getRegVal().intVal() = Mem_ub;
+                        ConstTaggedRegVal temp_regval;
+                        temp_regval.setTag(false);
+                        temp_regval.getRegVal().intVal() = Mem_ub;
+
+                        Rd_trv = temp_regval;
                     }});
                 0x5: lhu ({{ //ea_code
 
                     }}, {{ //comp_code
                         Rs1_trv;
                         getMemLE(pkt, Mem_uh, traceData);
 
-                        Rd_trv.getRegVal().intVal() = Mem_uh;
+                        ConstTaggedRegVal temp_regval;
+                        temp_regval.setTag(false);
+                        temp_regval.getRegVal().intVal() = Mem_uh;
+
+                        Rd_trv = temp_regval;
                     }});
                 0x6: lwu ({{ //ea_code
 
                     }}, {{ //comp_code
                         Rs1_trv;
                         getMemLE(pkt, Mem_uw, traceData);
 
-                        Rd_trv.getRegVal().intVal() = Mem_uw;
+                        ConstTaggedRegVal temp_regval;
+                        temp_regval.setTag(false);
+                        temp_regval.getRegVal().intVal() = Mem_uw;
+
+                        Rd_trv = temp_regval;
                     }});
             }
         }

diff --git a/src/arch/riscvcapstone/isa/formats/rnode.isa b/src/arch/riscvcapstone/isa/formats/rnode.isa
@@ -90,7 +90,7 @@ def template RNodeStoreConstructor {{
 
         hasNodeOp = true;
         flags[IsStore] = true;
-        flags[IsLoad] = false;
+        flags[IsLoad] = true;
     }
 }};
 
@@ -139,7 +139,7 @@ def template RNodeMemExecute {{
         assert(o3cpu);
 
         bool cwrld = o3cpu->cwrld[dyn_inst->threadNumber];
-        uint64_t emode = o3cpu->readMiscReg(CSR_EMODE, dyn_inst->threadNumber);
+        uint64_t emode = o3cpu->readMiscReg(MISCREG_EMODE, dyn_inst->threadNumber);
         if(cwrld || (!cwrld && emode)) {
             if(!Rs1.getTag()) {
                 return std::make_shared<IllegalInstFault>("Unexpected operand type (24)", machInst);
@@ -276,7 +276,7 @@ def template RNodeStoreExecute {{
         assert(o3cpu);
 
         bool cwrld = o3cpu->cwrld[dyn_inst->threadNumber];
-        uint64_t emode = o3cpu->readMiscReg(CSR_EMODE, dyn_inst->threadNumber);
+        uint64_t emode = o3cpu->readMiscReg(MISCREG_EMODE, dyn_inst->threadNumber);
         if(cwrld || (!cwrld && emode)) {
             if(!Rs1.getTag()) {
                 return std::make_shared<IllegalInstFault>(
@@ -336,7 +336,7 @@ def template RNodeStoreExecute {{
             return std::make_shared<IllegalInstFault>(
                     "Store address misaligned (6)", machInst);
 
-        Addr clen_aligned = EA & (sizeof(RegVal) - 1);
+        Addr clen_aligned = EA & ~(sizeof(RegVal) - 1);
         dyn_inst->initiateGetTag(clen_aligned);
         RegVal dummy;
         initiateMemRead(xc, traceData, clen_aligned, dummy, memAccessFlags);