Update debug insn encodings

Change-Id: I58726fadef90a728cf8d12bb0189738091eca99a
project-starch · Sep 23, 2023 · 4fc5197 · 4fc5197
1 parent ef523d6
commit 4fc5197
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Showing 2 changed files with 22 additions and 14 deletions.
diff --git a/src/arch/riscvcapstone/isa/decoder.isa b/src/arch/riscvcapstone/isa/decoder.isa
@@ -1550,31 +1550,31 @@ decode QUADRANT default Unknown::unknown() {
                     }});
                 }
                 format DropTest {
-                    0x1: dropt ({{
+                    0x10: dropt ({{
                         Rs1; Rs2; Rd;
                     }});
                 }
                 format RcUpdateTest {
-                    0x2: rcup ({{
+                    0x1: rcup ({{
                         Rs1; Rs2; Rd;
                     }});
                 }
                 format AllocTest {
-                    0x3: alloc ({{
+                    0x2: alloc ({{
                         Rs1; Rs2; Rd;
                     }});
                 }
                 format RevokeTest {
-                    0x4: revoket ({{
+                    0x3: revoket ({{
                         Rs1; Rs2; Rd;
                     }});
                 }
                 format ROp {
-                    0x5: capcreate ({{
+                    0x4: capcreate ({{
                         Rd_trv.setTag(true);
                         Rd_trv = Rd_trv; // just to make the dumb parser happy
                     }});
-                    0x6: captype ({{
+                    0x5: captype ({{
                         using namespace gem5::RiscvcapstoneISA::o3;
                         assert(Rd_trv.getTag());
                         //using CapType = gem5::RiscvcapstoneISA::o3::CapType;
@@ -1586,7 +1586,7 @@ decode QUADRANT default Unknown::unknown() {
                         Rd_trv.getRegVal().rawCapVal() = (uint128_t)rd_cap;
                         Rd_trv = Rd_trv; // just to make the dumb parser happy
                     }});
-                    0x7: capnode ({{
+                    0x6: capnode ({{
                         assert(Rd_trv.getTag());
                         using namespace gem5::RiscvcapstoneISA::o3;
                         //Rd_trv.getRegVal().val.cap.setNodeId(static_cast<NodeID>(Rs1));
@@ -1595,7 +1595,7 @@ decode QUADRANT default Unknown::unknown() {
                         Rd_trv.getRegVal().rawCapVal() = (uint128_t)rd_cap;
                         Rd_trv = Rd_trv; // just to make the dumb parser happy
                     }});
-                    0x8: capperm ({{
+                    0x7: capperm ({{
                         using namespace gem5::RiscvcapstoneISA::o3;
                         assert(Rd_trv.getTag());
                         //using CapPerm = gem5::RiscvcapstoneISA::o3::CapPerm;
@@ -1607,7 +1607,7 @@ decode QUADRANT default Unknown::unknown() {
                         Rd_trv.getRegVal().rawCapVal() = (uint128_t)rd_cap;
                         Rd_trv = Rd_trv; // just to make the dumb parser happy
                     }});
-                    0x9: capbound ({{
+                    0x8: capbound ({{
                         using namespace gem5::RiscvcapstoneISA::o3;
                         assert(Rd_trv.getTag());
                         //DPRINTFN("Set capability bound to (%llx, %llx)\n", Rs1, Rs2);
@@ -1617,7 +1617,7 @@ decode QUADRANT default Unknown::unknown() {
                         Rd_trv.getRegVal().rawCapVal() = (uint128_t)rd_cap;
                         Rd_trv = Rd_trv; // just to make the dumb parser happy
                     }});
-                    0xa: capprint ({{
+                    0x9: capprint ({{
                         //const RegVal& reg_val = Rs1_trv.getRegVal();
                         gem5::RiscvcapstoneISA::o3::Cap rs1_cap = Rs1_trv.getRegVal().capVal();
                         DPRINTFN("Capability (tag = %u) = (%llx, %llx), %llx, perm = %u, type = %u, node = %llu\n",
@@ -1640,14 +1640,14 @@ decode QUADRANT default Unknown::unknown() {
                     }});
                 }
                 format TagAccessStore {
-                    0xb: tagset ({{
+                    0xa: tagset ({{
                         EA = Rs1_ud;
 
                         dyn_inst->initiateSetTag(EA, Rs2_ud ? true : false);
                     }});
                 }
                 format TagAccess {
-                    0xc: tagget ({{
+                    0xb: tagget ({{
                         EA = Rs1_ud;
                         uint64_t _dd = Rs2;
 
@@ -1657,8 +1657,16 @@ decode QUADRANT default Unknown::unknown() {
                                     dyn_inst->getTagQueryRes(0));
                     }});
                 }
+                format ROp {
+                    0xc: cssetworld ({{
+                        Rs1_ud;
+                        //0xd: csonpartition
+                        //0xe: csseteh
+                        //0xf: csonnormaleh
+                    }});
+                }
                 format RNodeOp {
-                    0xf: printnode ({{
+                    0x11: printnode ({{
                         using namespace gem5::RiscvcapstoneISA::o3;
 
                         DynInst* dyn_inst = dynamic_cast<DynInst*>(xc);

diff --git a/src/arch/riscvcapstone/o3/iew.cc b/src/arch/riscvcapstone/o3/iew.cc
@@ -124,7 +124,7 @@ IEW::IEW(CPU *_cpu, const CapstoneBaseO3CPUParams &params)
     }
 
     assert(numThreads == 1); // FIXME: only supports a single thread for now
-    pcCaps[0].setAddresses(0, 0x1000000ULL, 0); // TODO: load this from the workload
+    pcCaps[0].setAddresses(0, 0xFFFFFFFFFULL, 0); // TODO: load this from the workload
     pcCaps[0].setPerm(CapPerm::RX);
     pcCaps[0].setType(CapType::LIN);