Fix bugs with instruction fetch; temporarily run everything in secure…

… world Change-Id: I3688dd90ae5a3582ab1246b7698cf222ef7c4f64
project-starch · Sep 22, 2023 · ef523d6 · ef523d6
1 parent a86a4ba
commit ef523d6
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Showing 4 changed files with 34 additions and 9 deletions.
diff --git a/src/arch/riscvcapstone/mmu.hh b/src/arch/riscvcapstone/mmu.hh
@@ -46,6 +46,9 @@
 
 #include "params/RiscvMMU.hh"
 
+#include "base/trace.hh"
+#include "debug/CapstoneMem.hh"
+
 namespace gem5
 {
 
@@ -81,8 +84,31 @@ class MMU : public BaseMMU
     }
 
     Fault translateAtomic(const RequestPtr& req, ThreadContext* tc, Mode mode) override {
-        //DPRINTF(CapstoneMem, "translate (atomic) %llx\n", req->getVaddr());
+        DPRINTF(CapstoneMem, "translate (atomic) %llx\n", req->getVaddr());
+        req->setPaddr(req->getVaddr()); // simply pass through
+        return NoFault;
+    }
+
+    void translateTiming(const RequestPtr& req, ThreadContext* tc,
+            Translation* translation, Mode mode) override {
+        if(tc->cwrld() == 1) {
+            DPRINTF(CapstoneMem, "translate %llx\n", req->getVaddr());
+            req->setPaddr(req->getVaddr()); // simply pass through
+            translation->finish(NoFault, req, tc, mode);
+        } else {
+            return getTlb(mode)->translateTiming(req, tc, translation, mode);
+        }
+    }
+
+    Fault translateFunctional(const RequestPtr& req, ThreadContext* tc, Mode mode) override {
         req->setPaddr(req->getVaddr()); // simply pass through
+
+        return NoFault;
+    }
+
+    void flushAll() override {} 
+
+    Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const override {
         return NoFault;
     }
 

diff --git a/src/arch/riscvcapstone/o3/cpu.cc b/src/arch/riscvcapstone/o3/cpu.cc
@@ -305,7 +305,7 @@ CPU::CPU(const CapstoneBaseO3CPUParams &params)
     if (!params.switched_out && interrupts.empty()) {
         fatal("O3CPU %s has no interrupt controller.\n"
               "Ensure createInterruptController() is called.\n", name());
-    }    
+    }
 }
 
 void

diff --git a/src/arch/riscvcapstone/process.cc b/src/arch/riscvcapstone/process.cc
@@ -73,11 +73,15 @@ RiscvProcess64::RiscvProcess64(const ProcessParams &params,
         loader::ObjectFile *objFile) :
         RiscvProcess(params, objFile)
 {
-    const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
+    //const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
+    //const Addr stack_base = 0x7FFFFFFF;
+    const Addr stack_base = 0x7ffffffffULL;
     const Addr max_stack_size = 8 * 1024 * 1024;
     const Addr next_thread_stack_base = stack_base - max_stack_size;
     const Addr brk_point = roundUp(image.maxAddr(), PageBytes);
-    const Addr mmap_end = 0x4000000000000000L;
+    //const Addr mmap_end = 0x4000000000000000L;
+    //const Addr mmap_end = 0x400000000L;
+    const Addr mmap_end = 0x400000000ULL;
     memState = std::make_shared<MemState>(this, brk_point, stack_base,
             max_stack_size, next_thread_stack_base, mmap_end);
 }

diff --git a/src/arch/riscvcapstone/tlb.cc b/src/arch/riscvcapstone/tlb.cc
@@ -339,11 +339,6 @@ TLB::translate(const RequestPtr &req, ThreadContext *tc,
 {
     delayed = false;
 
-    if(tc->cwrld() == 1) {
-        req->setPaddr(req->getVaddr());
-        return NoFault;
-    }
-
     if (FullSystem) {
         PrivilegeMode pmode = getMemPriv(tc, mode);
         SATP satp = tc->readMiscReg(MISCREG_SATP).intVal();