ise_hammer: 7v clock

docs/xilinx/virtex7/clock.rst

@@ -0,0 +1,41 @@
+.. _virtex7-clock:
+
+Clock interconnect
+##################
+
+.. todo:: describe this madness
+
+
+``HCLK``
+========
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-HCLK.html
+
+
+``CLK_BUFG``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CLK_BUFG.html
+
+
+``CLK_HROW``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CLK_HROW.html
+
+
+``CLK_BUFG_REBUF``
+==================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CLK_BUFG_REBUF.html
+
+
+``CLK_BALI_REBUF``
+==================
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CLK_BALI_REBUF.html

docs/xilinx/virtex7/cmt.rst

@@ -0,0 +1,20 @@
+.. _virtex7-cmt:
+
+Clock management tile
+#####################
+
+.. todo:: describe this madness
+
+
+``CMT``
+=======
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CMT.html
+
+
+``CMT_FIFO``
+============
+
+.. raw:: html
+   :file: ../gen/tile-xc7v-CMT_FIFO.html

docs/xilinx/virtex7/index.rst

@@ -13,5 +13,7 @@ Virtex 7
    bram
    dsp
    io
+   clock
+   cmt
    pcie
    pcie3

prjcombine_hammer/src/lib.rs

@@ -226,6 +226,7 @@ pub struct Session<'a, B: Backend> {
     backend: &'a B,
     pub debug: u8,
     pub dup_factor: u32,
+    pub max_threads: Option<usize>,
     batches: EntityVec<BatchId, Batch<B>>,
     fgens: Vec<FuzzerGenWrapper<'a, B>>,
 }
@@ -249,6 +250,7 @@ impl<'a, B: Backend> Session<'a, B> {
             backend,
             debug: 0,
             dup_factor: 3,
+            max_threads: None,
             batches: EntityVec::new(),
             fgens: vec![],
         }

prjcombine_hammer/src/run.rs

@@ -493,7 +493,9 @@ impl<'a, B: Backend> Session<'a, B> {
                 }
             }
         }
-        let nt = std::thread::available_parallelism().unwrap().get();
+        let nt = self
+            .max_threads
+            .unwrap_or_else(|| std::thread::available_parallelism().unwrap().get());
         std::thread::scope(|s| {
             for _ in 0..nt {
                 s.spawn(|| work(&queue));

prjcombine_ise_dump/src/partgen.rs

@@ -177,11 +177,7 @@ const PATTERNS: &[(&str, &str, &str)] = &[
         "[a-z]{2}[0-9]+",
         "virtex7",
     ),
-    (
-        "x[ca]7s[0-9]+",
-        "[a-z]{2}[gv][a-z][0-9]+",
-        "virtex7",
-    ),
+    ("x[ca]7s[0-9]+", "[a-z]{2}[gv][a-z][0-9]+", "virtex7"),
     ("xq7z[0-9]+", "[a-z]{2}g?[0-9]+", "virtex7"),
 ];
 

prjcombine_ise_hammer/src/backend.rs

@@ -758,6 +758,10 @@ impl<'a> Backend for IseBackend<'a> {
                 key = self.gen_key(&mut gopts);
             }
         }
+        if self.device.name.contains("7s15") || self.device.name.contains("7s6") {
+            // frankenstein ISE breaks non-compressed non-debug bitstreams on those for some reason
+            gopts.insert("COMPRESS".to_owned(), "".to_owned());
+        }
         let bitdata = run_bitgen(self.tc, &xdl, &gopts, &pcf, altvr).unwrap();
         parse(self.bs_geom, &bitdata, &key)
     }

prjcombine_ise_hammer/src/bram/virtex2.rs

@@ -13,7 +13,11 @@ use crate::{
     fuzz_enum, fuzz_multi, fuzz_one,
 };
 
-pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBackend<'a>) {
+pub fn add_fuzzers<'a>(
+    session: &mut Session<IseBackend<'a>>,
+    backend: &IseBackend<'a>,
+    devdata_only: bool,
+) {
     let grid_kind = match backend.edev {
         ExpandedDevice::Virtex2(ref edev) => edev.grid.kind,
         _ => unreachable!(),
@@ -32,6 +36,26 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
         GridKind::Spartan3A => "RAMB16BWE",
         _ => "RAMB16",
     };
+    if devdata_only {
+        if !grid_kind.is_virtex2() {
+            fuzz_one!(ctx, "Ibram_ddel", "!default", [
+                (global_mutex_site "BRAM"),
+                (mode bel_kind)
+            ], [
+                (global_opt "Ibram_ddel0", "0"),
+                (global_opt "Ibram_ddel1", "0")
+            ]);
+            fuzz_one!(ctx, "Ibram_wdel", "!default", [
+                (global_mutex_site "BRAM"),
+                (mode bel_kind)
+            ], [
+                (global_opt "Ibram_wdel0", "0"),
+                (global_opt "Ibram_wdel1", "0"),
+                (global_opt "Ibram_wdel2", "0")
+            ]);
+        }
+        return;
+    }
     match grid_kind {
         GridKind::Spartan3A | GridKind::Spartan3ADsp => {
             fuzz_one!(ctx, "PRESENT", "1", [
@@ -327,7 +351,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
     }
 }
 
-pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
+pub fn collect_fuzzers(ctx: &mut CollectorCtx, devdata_only: bool) {
     let grid_kind = match ctx.edev {
         ExpandedDevice::Virtex2(ref edev) => edev.grid.kind,
         _ => unreachable!(),
@@ -353,6 +377,68 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         GridKind::Spartan3A => "BRAM.S3A",
         GridKind::Spartan3ADsp => "BRAM.S3ADSP",
     };
+    fn filter_ab(diff: Diff) -> (Diff, Diff) {
+        (
+            Diff {
+                bits: diff
+                    .bits
+                    .iter()
+                    .filter(|&(&a, _)| a.tile < 2)
+                    .map(|(&a, &b)| (a, b))
+                    .collect(),
+            },
+            Diff {
+                bits: diff
+                    .bits
+                    .iter()
+                    .filter(|&(&a, _)| a.tile >= 2)
+                    .map(|(&a, &b)| (a, b))
+                    .collect(),
+            },
+        )
+    }
+    if devdata_only {
+        if !grid_kind.is_virtex2() {
+            let (adef, bdef) =
+                filter_ab(ctx.state.get_diff(tile, "BRAM", "Ibram_ddel", "!default"));
+            let adef = extract_bitvec_val(
+                ctx.tiledb.item(tile, "BRAM", "DDEL_A"),
+                &bitvec![0, 0],
+                !adef,
+            );
+            ctx.tiledb
+                .insert_device_data(&ctx.device.name, "BRAM:DDEL_A_DEFAULT", adef);
+            if grid_kind != GridKind::Spartan3 {
+                let bdef = extract_bitvec_val(
+                    ctx.tiledb.item(tile, "BRAM", "DDEL_B"),
+                    &bitvec![0, 0],
+                    !bdef,
+                );
+                ctx.tiledb
+                    .insert_device_data(&ctx.device.name, "BRAM:DDEL_B_DEFAULT", bdef);
+            }
+
+            let (adef, bdef) =
+                filter_ab(ctx.state.get_diff(tile, "BRAM", "Ibram_wdel", "!default"));
+            let adef = extract_bitvec_val(
+                ctx.tiledb.item(tile, "BRAM", "WDEL_A"),
+                &bitvec![0, 0, 0],
+                !adef,
+            );
+            ctx.tiledb
+                .insert_device_data(&ctx.device.name, "BRAM:WDEL_A_DEFAULT", adef);
+            if grid_kind != GridKind::Spartan3 {
+                let bdef = extract_bitvec_val(
+                    ctx.tiledb.item(tile, "BRAM", "WDEL_B"),
+                    &bitvec![0, 0, 0],
+                    !bdef,
+                );
+                ctx.tiledb
+                    .insert_device_data(&ctx.device.name, "BRAM:WDEL_B_DEFAULT", bdef);
+            }
+        }
+        return;
+    }
     let mut present = ctx.state.get_diff(tile, "BRAM", "PRESENT", "1");
     let mut diffs_data = vec![];
     let mut diffs_datap = vec![];
@@ -479,26 +565,6 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         }
     }
     if !grid_kind.is_virtex2() {
-        fn filter_ab(diff: Diff) -> (Diff, Diff) {
-            (
-                Diff {
-                    bits: diff
-                        .bits
-                        .iter()
-                        .filter(|&(&a, _)| a.tile < 2)
-                        .map(|(&a, &b)| (a, b))
-                        .collect(),
-                },
-                Diff {
-                    bits: diff
-                        .bits
-                        .iter()
-                        .filter(|&(&a, _)| a.tile >= 2)
-                        .map(|(&a, &b)| (a, b))
-                        .collect(),
-                },
-            )
-        }
         let (a0, b0) = filter_ab(ctx.state.get_diff(tile, "BRAM", "Ibram_ddel0", "1"));
         let (a1, b1) = filter_ab(ctx.state.get_diff(tile, "BRAM", "Ibram_ddel1", "1"));
         let (adef, bdef) = filter_ab(ctx.state.get_diff(tile, "BRAM", "Ibram_ddel", "!default"));

prjcombine_ise_hammer/src/clk.rs

@@ -4,3 +4,4 @@ pub mod virtex2;
 pub mod virtex4;
 pub mod virtex5;
 pub mod virtex6;
+pub mod virtex7;

prjcombine_ise_hammer/src/clk/spartan6.rs

@@ -1,20 +1,44 @@
 use std::collections::HashSet;
 
+use bitvec::vec::BitVec;
 use prjcombine_hammer::Session;
 use prjcombine_int::db::{BelId, Dir};
 use prjcombine_spartan6::grid::Gts;
+use prjcombine_types::TileItemKind;
 use prjcombine_xilinx_geom::ExpandedDevice;
 use unnamed_entity::EntityId;
 
 use crate::{
     backend::IseBackend,
-    diff::{xlat_bit, xlat_bit_wide, xlat_enum, xlat_enum_ocd, CollectorCtx, OcdMode},
+    diff::{
+        xlat_bit, xlat_bit_wide, xlat_enum, xlat_enum_ocd, CollectorCtx,
+        OcdMode,
+    },
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits, TileKV},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_one, fuzz_one_extras,
 };
 
-pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBackend<'a>) {
+pub fn add_fuzzers<'a>(
+    session: &mut Session<IseBackend<'a>>,
+    backend: &IseBackend<'a>,
+    devdata_only: bool,
+) {
+    if devdata_only {
+        let ctx = FuzzCtx::new(
+            session,
+            backend,
+            "PCILOGICSE",
+            "PCILOGICSE",
+            TileBits::MainAuto,
+        );
+        fuzz_one!(ctx, "PRESENT", "1", [
+            (no_global_opt "PCI_CE_DELAY_LEFT")
+        ], [
+            (mode "PCILOGICSE")
+        ]);
+        return;
+    }
     let ExpandedDevice::Spartan6(edev) = backend.edev else {
         unreachable!()
     };
@@ -725,10 +749,32 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
     }
 }
 
-pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
+pub fn collect_fuzzers(ctx: &mut CollectorCtx, devdata_only: bool) {
     let ExpandedDevice::Spartan6(edev) = ctx.edev else {
         unreachable!()
     };
+    if devdata_only {
+        let tile = "PCILOGICSE";
+        let bel = "PCILOGICSE";
+        let default = ctx.state.get_diff(tile, bel, "PRESENT", "1");
+        let item = ctx.tiledb.item(tile, bel, "PCI_CE_DELAY");
+        let val: BitVec = item
+            .bits
+            .iter()
+            .map(|bit| default.bits.contains_key(bit))
+            .collect();
+        let TileItemKind::Enum { ref values } = item.kind else {
+            unreachable!()
+        };
+        for (k, v) in values {
+            if *v == val {
+                ctx.tiledb
+                    .insert_device_data(&ctx.device.name, "PCI_CE_DELAY", k.clone());
+                break;
+            }
+        }
+        return;
+    }
     {
         let tile = "HCLK";
         let bel = "HCLK";