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sli v7 bs parsing
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@wanda-phi
wanda-phi committed Sep 17, 2024
1 parent 3473c13 commit 1bb64bd
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Showing 13 changed files with 231 additions and 84 deletions.
2 changes: 1 addition & 1 deletion Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,7 @@ members = [
"prjcombine_sdf",
"prjcombine_xc9500",
"prjcombine_xpla3",
"prjcombine_xc2c",
"prjcombine_xc2c", "prjcombine_xilinx_rdis",
]
resolver = "2"

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30 changes: 16 additions & 14 deletions prjcombine_ise_dump/src/bin/dump_ise_parts.rs
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Expand Up @@ -79,20 +79,22 @@ fn main() -> Result<(), Box<dyn Error>> {
"virtex4" => vec!["virtex4", "qvirtex4", "qrvirtex4"],
"virtex5" => vec!["virtex5", "qvirtex5"],
"virtex6" => vec!["virtex6", "virtex6l", "qvirtex6", "qvirtex6l"],
"7series" => vec![
"artix7",
"artix7l",
"aartix7",
"qartix7",
"kintex7",
"kintex7l",
"qkintex7",
"qkintex7l",
"virtex7",
"qvirtex7",
"zynq",
"azynq",
"qzynq",
"virtex7" => vec![
"spartan7",
"aspartan7",
// "artix7",
// "artix7l",
// "aartix7",
// "qartix7",
// "kintex7",
// "kintex7l",
// "qkintex7",
// "qkintex7l",
// "virtex7",
// "qvirtex7",
// "zynq",
// "azynq",
// "qzynq",
],
_ => bail!("unknown family {}", family),
});
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11 changes: 8 additions & 3 deletions prjcombine_ise_dump/src/partgen.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -170,14 +170,19 @@ const PATTERNS: &[(&str, &str, &str)] = &[
(
"x[ca]7(?:[akvz]|v[xh])[0-9]+[st]?[li]?",
"[a-z]{2}[gv][0-9]+",
"7series",
"virtex7",
),
(
"xq7(?:[akv]|v[xh])[0-9]+t?[li]?",
"[a-z]{2}[0-9]+",
"7series",
"virtex7",
),
("xq7z[0-9]+", "[a-z]{2}g?[0-9]+", "7series"),
(
"x[ca]7s[0-9]+",
"[a-z]{2}[gv][a-z][0-9]+",
"virtex7",
),
("xq7z[0-9]+", "[a-z]{2}g?[0-9]+", "virtex7"),
];

pub fn split_partname(s: &str) -> Option<(&str, &str, &str)> {
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2 changes: 1 addition & 1 deletion prjcombine_rawdump/src/bin/rd2html.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -3572,7 +3572,7 @@ fn main() -> Result<(), Box<dyn Error>> {
"virtex4" => (VIRTEX4_TILES, false),
"virtex5" => (VIRTEX5_TILES, true),
"virtex6" => (VIRTEX6_TILES, true),
"7series" => (VIRTEX7_TILES, true),
"virtex7" => (VIRTEX7_TILES, true),
"ultrascale" => (ULTRASCALE_TILES, true),
"ultrascaleplus" => (ULTRASCALEPLUS_TILES, true),
"versal" => (VERSAL_TILES, true),
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4 changes: 2 additions & 2 deletions prjcombine_v2xdl_verify/src/main.rs
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Expand Up @@ -210,7 +210,7 @@ fn get_spartan6_tests() -> Vec<Test> {
res
}

fn get_7series_tests() -> Vec<Test> {
fn get_virtex7_tests() -> Vec<Test> {
let mut res = Vec::new();
let mut ctx = TestGenCtx::new();
let part = "xc7k70t-1-fbg676";
Expand Down Expand Up @@ -251,7 +251,7 @@ fn main() -> Result<(), Box<dyn Error>> {
"virtex4" => get_virtex4_tests(),
"virtex5" => get_virtex5_tests(),
"virtex6" => get_virtex6_tests(),
"7series" => get_7series_tests(),
"virtex7" => get_virtex7_tests(),
_ => panic!("unknown family {family}"),
};
tests.par_iter().for_each(|t| {
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18 changes: 15 additions & 3 deletions prjcombine_virtex4/src/expand/virtex7.rs
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Expand Up @@ -2073,7 +2073,11 @@ impl DieExpander<'_, '_, '_> {
self.frame_info.push(FrameInfo {
addr: FrameAddr {
typ: 0,
region: (reg - self.grid.reg_cfg) as i32,
region: if self.grid.regs == 1 {
0
} else {
(reg - self.grid.reg_cfg) as i32
},
major: col.to_idx() as u32,
minor,
},
Expand All @@ -2098,7 +2102,11 @@ impl DieExpander<'_, '_, '_> {
self.frame_info.push(FrameInfo {
addr: FrameAddr {
typ: 0,
region: (reg - self.grid.reg_cfg) as i32,
region: if self.grid.regs == 1 {
0
} else {
(reg - self.grid.reg_cfg) as i32
},
major: col.to_idx() as u32,
minor,
},
Expand All @@ -2124,7 +2132,11 @@ impl DieExpander<'_, '_, '_> {
self.frame_info.push(FrameInfo {
addr: FrameAddr {
typ: 1,
region: (reg - self.grid.reg_cfg) as i32,
region: if self.grid.regs == 1 {
0
} else {
(reg - self.grid.reg_cfg) as i32
},
major,
minor,
},
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12 changes: 12 additions & 0 deletions prjcombine_virtex_bitstream/src/packet.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,7 @@ pub enum Packet {
CmdMfwr,
CmdDGHigh,
CmdStart,
CmdShutdown,
CmdRcrc,
CmdSwitch,
CmdGRestore,
Expand Down Expand Up @@ -74,6 +75,7 @@ pub enum Packet {
Trim(u32),
Dwc(u32),
Fdri(Vec<u8>),
Bout(Vec<u8>),
EncFdri(Vec<u8>),
BugFdri(Vec<u8>),
}
Expand Down Expand Up @@ -196,6 +198,10 @@ impl<'a> PacketParser<'a> {
pub fn peek(&self) -> Option<Packet> {
self.clone().next()
}

pub fn desync(&mut self) {
self.sync = false;
}
}

impl<'a> Iterator for PacketParser<'a> {
Expand Down Expand Up @@ -267,6 +273,7 @@ impl<'a> Iterator for PacketParser<'a> {
}
9 => Some(Packet::CmdSwitch),
10 => Some(Packet::CmdGRestore),
11 => Some(Packet::CmdShutdown),
13 => Some(Packet::CmdDesynch),
val => panic!("unk cmd: {val}"),
},
Expand Down Expand Up @@ -519,6 +526,7 @@ impl<'a> Iterator for PacketParser<'a> {
}
9 => Some(Packet::CmdSwitch),
10 => Some(Packet::CmdGRestore),
11 => Some(Packet::CmdShutdown),
13 => Some(Packet::CmdDesynch),
val => panic!("unk cmd: {val}"),
},
Expand Down Expand Up @@ -621,6 +629,7 @@ impl<'a> Iterator for PacketParser<'a> {
}
(0x1b, 1) if is_v4 => Some(Packet::Trim(get_val(0))),
(0x1c, 1) if is_v4 => Some(Packet::Unk1c(get_val(0))),
(0x1e, 0) => continue,
_ => panic!("unk write: {reg} times {num}"),
}
} else if (ph >> 27) == 7 {
Expand Down Expand Up @@ -677,6 +686,9 @@ impl<'a> Iterator for PacketParser<'a> {
Some(Packet::Fdri(src_data[dpos..epos].to_vec()))
}
}
0x1e => {
Some(Packet::Bout(src_data[dpos..epos].to_vec()))
}
_ => panic!("unk long write: {reg} times {num}"),
}
} else if (ph >> 27) == 0xb {
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