5v PPC/EMAC/PCIE

docs/xilinx/virtex5/emac.rst

@@ -0,0 +1,9 @@
+Ethernet MACs
+#############
+
+
+Bitstream
+=========
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-EMAC.html

docs/xilinx/virtex5/index.rst

@@ -11,3 +11,6 @@ Xilinx Virtex 5 FPGAs
    clb
    bram
    dsp
+   ppc
+   emac
+   pcie

docs/xilinx/virtex5/pcie.rst

@@ -0,0 +1,9 @@
+PCI Express cores
+#################
+
+
+Bitstream
+=========
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-PCIE.html

docs/xilinx/virtex5/ppc.rst

@@ -0,0 +1,9 @@
+PowerPC cores
+#############
+
+
+Bitstream
+=========
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-PPC.html

prjcombine_ise_hammer/src/diff.rs

@@ -569,6 +569,12 @@ pub fn xlat_bool(diff0: Diff, diff1: Diff) -> TileItem<FeatureBit> {
 }
 
 impl<'a, 'b: 'a> CollectorCtx<'a, 'b> {
+    pub fn has_tile(&self, tile: &str) -> bool {
+        let egrid = self.edev.egrid();
+        let node = egrid.db.get_node(tile);
+        !egrid.node_index[node].is_empty()
+    }
+
     #[must_use]
     pub fn extract_bitvec(
         &mut self,

prjcombine_ise_hammer/src/emac.rs

@@ -0,0 +1 @@
+pub mod virtex5;

prjcombine_ise_hammer/src/emac/virtex5.rs

@@ -0,0 +1,149 @@
+use prjcombine_hammer::Session;
+
+use crate::{
+    backend::IseBackend, diff::CollectorCtx, fgen::TileBits, fuzz::FuzzCtx, fuzz_enum, fuzz_inv,
+    fuzz_multi_attr_hex, fuzz_one,
+};
+
+const EMAC_INVPINS: &[&str] = &[
+    "CLIENTEMAC0RXCLIENTCLKIN",
+    "CLIENTEMAC0TXCLIENTCLKIN",
+    "CLIENTEMAC1RXCLIENTCLKIN",
+    "CLIENTEMAC1TXCLIENTCLKIN",
+    "DCREMACCLK",
+    "HOSTCLK",
+    "PHYEMAC0GTXCLK",
+    "PHYEMAC0MCLKIN",
+    "PHYEMAC0MIITXCLK",
+    "PHYEMAC0RXCLK",
+    "PHYEMAC0TXGMIIMIICLKIN",
+    "PHYEMAC1GTXCLK",
+    "PHYEMAC1MCLKIN",
+    "PHYEMAC1MIITXCLK",
+    "PHYEMAC1RXCLK",
+    "PHYEMAC1TXGMIIMIICLKIN",
+];
+
+const EMAC_BOOL_ATTRS: &[&str] = &[
+    "EMAC0_RXHALFDUPLEX",
+    "EMAC0_RXVLAN_ENABLE",
+    "EMAC0_RX_ENABLE",
+    "EMAC0_RXINBANDFCS_ENABLE",
+    "EMAC0_RXJUMBOFRAME_ENABLE",
+    "EMAC0_RXRESET",
+    "EMAC0_TXIFGADJUST_ENABLE",
+    "EMAC0_TXHALFDUPLEX",
+    "EMAC0_TXVLAN_ENABLE",
+    "EMAC0_TX_ENABLE",
+    "EMAC0_TXINBANDFCS_ENABLE",
+    "EMAC0_TXJUMBOFRAME_ENABLE",
+    "EMAC0_TXRESET",
+    "EMAC0_TXFLOWCTRL_ENABLE",
+    "EMAC0_RXFLOWCTRL_ENABLE",
+    "EMAC0_LTCHECK_DISABLE",
+    "EMAC0_ADDRFILTER_ENABLE",
+    "EMAC0_RX16BITCLIENT_ENABLE",
+    "EMAC0_TX16BITCLIENT_ENABLE",
+    "EMAC0_HOST_ENABLE",
+    "EMAC0_1000BASEX_ENABLE",
+    "EMAC0_SGMII_ENABLE",
+    "EMAC0_RGMII_ENABLE",
+    "EMAC0_SPEED_LSB",
+    "EMAC0_SPEED_MSB",
+    "EMAC0_MDIO_ENABLE",
+    "EMAC0_PHYLOOPBACKMSB",
+    "EMAC0_PHYPOWERDOWN",
+    "EMAC0_PHYISOLATE",
+    "EMAC0_PHYINITAUTONEG_ENABLE",
+    "EMAC0_PHYRESET",
+    "EMAC0_CONFIGVEC_79",
+    "EMAC0_UNIDIRECTION_ENABLE",
+    "EMAC0_GTLOOPBACK",
+    "EMAC0_BYTEPHY",
+    "EMAC0_USECLKEN",
+    "EMAC1_RXHALFDUPLEX",
+    "EMAC1_RXVLAN_ENABLE",
+    "EMAC1_RX_ENABLE",
+    "EMAC1_RXINBANDFCS_ENABLE",
+    "EMAC1_RXJUMBOFRAME_ENABLE",
+    "EMAC1_RXRESET",
+    "EMAC1_TXIFGADJUST_ENABLE",
+    "EMAC1_TXHALFDUPLEX",
+    "EMAC1_TXVLAN_ENABLE",
+    "EMAC1_TX_ENABLE",
+    "EMAC1_TXINBANDFCS_ENABLE",
+    "EMAC1_TXJUMBOFRAME_ENABLE",
+    "EMAC1_TXRESET",
+    "EMAC1_TXFLOWCTRL_ENABLE",
+    "EMAC1_RXFLOWCTRL_ENABLE",
+    "EMAC1_LTCHECK_DISABLE",
+    "EMAC1_ADDRFILTER_ENABLE",
+    "EMAC1_RX16BITCLIENT_ENABLE",
+    "EMAC1_TX16BITCLIENT_ENABLE",
+    "EMAC1_HOST_ENABLE",
+    "EMAC1_1000BASEX_ENABLE",
+    "EMAC1_SGMII_ENABLE",
+    "EMAC1_RGMII_ENABLE",
+    "EMAC1_SPEED_LSB",
+    "EMAC1_SPEED_MSB",
+    "EMAC1_MDIO_ENABLE",
+    "EMAC1_PHYLOOPBACKMSB",
+    "EMAC1_PHYPOWERDOWN",
+    "EMAC1_PHYISOLATE",
+    "EMAC1_PHYINITAUTONEG_ENABLE",
+    "EMAC1_PHYRESET",
+    "EMAC1_CONFIGVEC_79",
+    "EMAC1_UNIDIRECTION_ENABLE",
+    "EMAC1_GTLOOPBACK",
+    "EMAC1_BYTEPHY",
+    "EMAC1_USECLKEN",
+];
+
+const EMAC_HEX_ATTRS: &[(&str, usize)] = &[
+    ("EMAC0_DCRBASEADDR", 8),
+    ("EMAC0_FUNCTION", 3),
+    ("EMAC0_LINKTIMERVAL", 9),
+    ("EMAC0_PAUSEADDR", 48),
+    ("EMAC0_UNICASTADDR", 48),
+    ("EMAC1_DCRBASEADDR", 8),
+    ("EMAC1_FUNCTION", 3),
+    ("EMAC1_LINKTIMERVAL", 9),
+    ("EMAC1_PAUSEADDR", 48),
+    ("EMAC1_UNICASTADDR", 48),
+];
+
+pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBackend<'a>) {
+    let Some(ctx) = FuzzCtx::try_new(session, backend, "EMAC", "EMAC", TileBits::MainAuto) else {
+        return;
+    };
+
+    fuzz_one!(ctx, "PRESENT", "1", [], [(mode "TEMAC")]);
+
+    for &pin in EMAC_INVPINS {
+        fuzz_inv!(ctx, pin, [(mode "TEMAC")]);
+    }
+    for &attr in EMAC_BOOL_ATTRS {
+        fuzz_enum!(ctx, attr, ["FALSE", "TRUE"], [(mode "TEMAC")]);
+    }
+    for &(attr, width) in EMAC_HEX_ATTRS {
+        fuzz_multi_attr_hex!(ctx, attr, width, [(mode "TEMAC")]);
+    }
+}
+
+pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
+    if !ctx.has_tile("EMAC") {
+        return;
+    }
+    let tile = "EMAC";
+    let bel = "EMAC";
+    ctx.state.get_diff(tile, bel, "PRESENT", "1").assert_empty();
+    for &pin in EMAC_INVPINS {
+        ctx.collect_inv(tile, bel, pin);
+    }
+    for &attr in EMAC_BOOL_ATTRS {
+        ctx.collect_enum_bool(tile, bel, attr, "FALSE", "TRUE");
+    }
+    for &(attr, _) in EMAC_HEX_ATTRS {
+        ctx.collect_bitvec(tile, bel, attr, "");
+    }
+}

prjcombine_ise_hammer/src/main.rs

@@ -26,6 +26,7 @@ mod io;
 mod misc;
 mod pcie;
 mod ppc;
+mod emac;
 mod tiledb;
 
 use backend::IseBackend;
@@ -188,9 +189,9 @@ fn main() -> Result<(), Box<dyn Error>> {
                     // TODO: io
                     // TODO: dcm
                     // TODO: pll
-                    // TODO: ppc
-                    // TODO: pcie
-                    // TODO: emac
+                    ppc::virtex5::add_fuzzers(&mut hammer, &backend);
+                    emac::virtex5::add_fuzzers(&mut hammer, &backend);
+                    pcie::virtex5::add_fuzzers(&mut hammer, &backend);
                     // TODO: gtp
                     // TODO: gtx
                 }
@@ -308,6 +309,9 @@ fn main() -> Result<(), Box<dyn Error>> {
                     clb::virtex5::collect_fuzzers(&mut ctx);
                     bram::virtex5::collect_fuzzers(&mut ctx);
                     dsp::virtex5::collect_fuzzers(&mut ctx);
+                    ppc::virtex5::collect_fuzzers(&mut ctx);
+                    emac::virtex5::collect_fuzzers(&mut ctx);
+                    pcie::virtex5::collect_fuzzers(&mut ctx);
                 }
                 prjcombine_virtex4::grid::GridKind::Virtex6 => {
                     clb::virtex5::collect_fuzzers(&mut ctx);

prjcombine_ise_hammer/src/pcie.rs

@@ -1 +1,2 @@
-pub mod spartan6;
+pub mod spartan6;
+pub mod virtex5;