ise_hammer: 5v BRAM

prjunnamed · Jul 10, 2024 · c00ba3f · c00ba3f
1 parent 37a1878
commit c00ba3f
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Showing 7 changed files with 1,411 additions and 2 deletions.
diff --git a/databases/xc5v-tiledb.json b/databases/xc5v-tiledb.json
diff --git a/docs/xilinx/virtex5/bram.rst b/docs/xilinx/virtex5/bram.rst
@@ -0,0 +1,9 @@
+Block RAM
+#########
+
+
+Bitstream
+=========
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc5v-BRAM.html
diff --git a/docs/xilinx/virtex5/index.rst b/docs/xilinx/virtex5/index.rst
@@ -9,4 +9,5 @@ Xilinx Virtex 5 FPGAs
 
    int
    clb
+   bram
    dsp
diff --git a/prjcombine_ise_hammer/src/bram.rs b/prjcombine_ise_hammer/src/bram.rs
@@ -2,3 +2,4 @@ pub mod virtex;
 pub mod virtex2;
 pub mod spartan6;
 pub mod virtex4;
+pub mod virtex5;
-Original file line number
+Diff line change
@@ Expand Up / @@ -9,4 +9,5 @@ Xilinx Virtex 5 FPGAs @@
        int
        clb
+       bram
        dsp