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    • stac-top

      Public
      The SRAM timing analysis chip for verifying SRAMs generated by SRAM22
      Scala
      BSD 3-Clause "New" or "Revised" License
      0402Updated Nov 11, 2024Nov 11, 2024
    • chipyard

      Public
      An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
      Scala
      BSD 3-Clause "New" or "Revised" License
      6521.6k18432Updated Nov 11, 2024Nov 11, 2024
    • SystemVerilog
      BSD 3-Clause "New" or "Revised" License
      0200Updated Nov 10, 2024Nov 10, 2024
    • gemmini

      Public
      Berkeley's Spatial Array Generator
      Scala
      Other
      1708117812Updated Nov 10, 2024Nov 10, 2024
    • radiance

      Public
      Rocket Chip Generator
      SystemVerilog
      Other
      1.1k100Updated Nov 10, 2024Nov 10, 2024
    • SuperNoVA

      Public
      su su su supernova
      Scala
      0100Updated Nov 10, 2024Nov 10, 2024
    • ra-isam2

      Public
      Fork of GTSAM. Implements resource-aware ISAM2 for SuperNoVA
      C++
      Other
      0000Updated Nov 9, 2024Nov 9, 2024
    • Chisel RISC-V Vector 1.0 Implementation
      Assembly
      BSD 3-Clause "New" or "Revised" License
      45020Updated Nov 8, 2024Nov 8, 2024
    • C
      BSD 3-Clause "New" or "Revised" License
      13031Updated Nov 8, 2024Nov 8, 2024
    • Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
      C
      Other
      405268Updated Nov 8, 2024Nov 8, 2024
    • A submodule of Chipyard https://github.com/ucb-bar/chipyard
      HTML
      7831Updated Nov 6, 2024Nov 6, 2024
    • A submodule of Chipyard https://github.com/ucb-bar/chipyard
      HTML
      7100Updated Nov 3, 2024Nov 3, 2024
    • AuRORA

      Public
      Virtualized Accelerator Orchestration for Multi-Tenant Workloads
      C
      1820Updated Nov 2, 2024Nov 2, 2024
    • hammer

      Public
      Hammer: Highly Agile Masks Made Effortlessly from RTL
      Python
      BSD 3-Clause "New" or "Revised" License
      5925520319Updated Nov 1, 2024Nov 1, 2024
    • shuttle

      Public
      A Rocket-based RISC-V superscalar in-order core
      Scala
      22700Updated Oct 29, 2024Oct 29, 2024
    • Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.
      C
      32201Updated Oct 29, 2024Oct 29, 2024
    • matlib

      Public
      Matrix Library for RISC-V Accelerators
      Python
      BSD 3-Clause "New" or "Revised" License
      2100Updated Oct 28, 2024Oct 28, 2024
    • Scala
      0200Updated Oct 24, 2024Oct 24, 2024
    • Model-predictive control for microcontrollers (fork mapping tinyMPC to gemmini or other HW accelerators)
      C++
      MIT License
      74300Updated Oct 23, 2024Oct 23, 2024
    • G1-Demos

      Public
      Python
      MIT License
      1000Updated Oct 23, 2024Oct 23, 2024
    • IsaacLabG1Extension

      Public template
      External extenstion template based on Isaac Lab
      Python
      MIT License
      42000Updated Oct 21, 2024Oct 21, 2024
    • IsaacLab

      Public
      Unified framework for robot learning built on NVIDIA Isaac Sim
      Python
      Other
      902000Updated Oct 21, 2024Oct 21, 2024
    • Scala
      BSD 3-Clause "New" or "Revised" License
      5980154Updated Oct 17, 2024Oct 17, 2024
    • Prebuilt RISC-V GCC Toolchains for Linux
      0000Updated Oct 15, 2024Oct 15, 2024
    • dosa

      Public
      DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators
      Python
      BSD 2-Clause "Simplified" License
      11410Updated Oct 10, 2024Oct 10, 2024
    • Scala
      BSD 3-Clause "New" or "Revised" License
      0000Updated Oct 10, 2024Oct 10, 2024
    • Rust
      0200Updated Oct 9, 2024Oct 9, 2024
    • Python
      Other
      0000Updated Oct 7, 2024Oct 7, 2024
    • RoSE

      Public
      A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.
      Python
      BSD 3-Clause "New" or "Revised" License
      43601Updated Sep 27, 2024Sep 27, 2024
    • Chisel wrapper for the SpinalHDL VexiiRiscv CPU implementation, implementing Chipyard compatibility
      Scala
      BSD 3-Clause "New" or "Revised" License
      0000Updated Sep 26, 2024Sep 26, 2024