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Chisel wrapper for the SpinalHDL VexiiRiscv CPU implementation, implementing Chipyard compatibility

BSD-3-Clause license

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Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
VexiiRiscv @ 194adb4		VexiiRiscv @ 194adb4
src/main/scala/vexiiriscv		src/main/scala/vexiiriscv
.gitignore		.gitignore
.gitmodules		.gitmodules
LICENSE		LICENSE
README.md		README.md

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Chipyard/Rocket-chip Tile Wrapper for the VexiiRiscv core

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Chisel wrapper for the SpinalHDL VexiiRiscv CPU implementation, implementing Chipyard compatibility

BSD-3-Clause license

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Scala 100.0%