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SIMD clang builtin fixes #101

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Dec 28, 2023
Merged

SIMD clang builtin fixes #101

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54fe511
[RISCV][CV-SIMD] Immediate arg of shuffle.sci.* builtins to const fold
PaoloS02 Dec 27, 2023
99167f3
[RISCV][CV-SIMD] Check value range of constant operands of simd built…
PaoloS02 Dec 27, 2023
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4 changes: 2 additions & 2 deletions clang/include/clang/Basic/BuiltinsRISCVCOREV.def
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Original file line number Diff line number Diff line change
Expand Up @@ -112,8 +112,8 @@ TARGET_BUILTIN(simd_insert_h, "UZiUZiUZiIUc", "nc", "xcvsimd")
TARGET_BUILTIN(simd_insert_b, "UZiUZiUZiIUc", "nc", "xcvsimd")
TARGET_BUILTIN(simd_shuffle_h, "UZiUZiUZi", "nc", "xcvsimd")
TARGET_BUILTIN(simd_shuffle_b, "UZiUZiUZi", "nc", "xcvsimd")
TARGET_BUILTIN(simd_shuffle_sci_h, "UZiUZiUZi", "nc", "xcvsimd")
TARGET_BUILTIN(simd_shuffle_sci_b, "UZiUZiUZi", "nc", "xcvsimd")
TARGET_BUILTIN(simd_shuffle_sci_h, "UZiUZiIUc", "nc", "xcvsimd")
TARGET_BUILTIN(simd_shuffle_sci_b, "UZiUZiIUc", "nc", "xcvsimd")
TARGET_BUILTIN(simd_shuffle2_h, "UZiUZiUZiUZi", "nc", "xcvsimd")
TARGET_BUILTIN(simd_shuffle2_b, "UZiUZiUZiUZi", "nc", "xcvsimd")
TARGET_BUILTIN(simd_packhi_h, "UZiUZiUZi", "nc", "xcvsimd")
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10 changes: 10 additions & 0 deletions clang/lib/Sema/SemaChecking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4468,6 +4468,9 @@ bool Sema::CheckRISCVCOREVBuiltinFunctionCall(unsigned BuiltinID,
// range check them here.
switch (BuiltinID) {
default: return false;
case RISCVCOREV::BI__builtin_riscv_cv_simd_add_h:
case RISCVCOREV::BI__builtin_riscv_cv_simd_sub_h:
return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3);
case RISCVCOREV::BI__builtin_riscv_cv_simd_extract_h:
case RISCVCOREV::BI__builtin_riscv_cv_simd_extractu_h:
return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
Expand All @@ -4478,6 +4481,13 @@ bool Sema::CheckRISCVCOREVBuiltinFunctionCall(unsigned BuiltinID,
return SemaBuiltinConstantArgRange(TheCall, 2, 0, 1);
case RISCVCOREV::BI__builtin_riscv_cv_simd_insert_b:
return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3);
case RISCVCOREV::BI__builtin_riscv_cv_simd_shuffle_sci_h:
return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3);
case RISCVCOREV::BI__builtin_riscv_cv_simd_cplxmul_r:
case RISCVCOREV::BI__builtin_riscv_cv_simd_cplxmul_i:
return SemaBuiltinConstantArgRange(TheCall, 3, 0, 3);
case RISCVCOREV::BI__builtin_riscv_cv_simd_subrotmj:
return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3);
}
}

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48 changes: 48 additions & 0 deletions clang/test/CodeGen/RISCV/corev-intrinsics/simd-errors.c
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Original file line number Diff line number Diff line change
@@ -1,6 +1,22 @@
// RUN: %clang_cc1 %s -triple=riscv32 -target-feature +xcvsimd -fsyntax-only -verify
#include <stdint.h>

uint32_t test_add_h(uint32_t a, uint32_t b) {
return __builtin_riscv_cv_simd_add_h(a, b, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
}

uint32_t test_add_h_negative(uint32_t a, uint32_t b) {
return __builtin_riscv_cv_simd_add_h(a, b, -1); // expected-error {{argument value 255 is outside the valid range [0, 3]}}
}

uint32_t test_sub_h(uint32_t a, uint32_t b) {
return __builtin_riscv_cv_simd_sub_h(a, b, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
}

uint32_t test_sub_h_negative(uint32_t a, uint32_t b) {
return __builtin_riscv_cv_simd_sub_h(a, b, -1); // expected-error {{argument value 255 is outside the valid range [0, 3]}}
}

uint32_t test_extract_h(uint32_t a) {
return __builtin_riscv_cv_simd_extract_h(a, 2); // expected-error {{argument value 2 is outside the valid range [0, 1]}}
}
Expand Down Expand Up @@ -48,3 +64,35 @@ uint32_t test_insert_b(uint32_t dst, uint8_t a) {
uint32_t test_insert_b_negative(uint32_t dst, uint8_t a) {
return __builtin_riscv_cv_simd_insert_b(dst, a, -1); // expected-error {{argument value 255 is outside the valid range [0, 3]}}
}

uint32_t test_shuffle_sci_h(uint32_t a) {
return __builtin_riscv_cv_simd_shuffle_sci_h(a, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
}

uint32_t test_shuffle_sci_h_negative(uint32_t a) {
return __builtin_riscv_cv_simd_shuffle_sci_h(a, -1); // expected-error {{argument value 255 is outside the valid range [0, 3]}}
}

uint32_t test_cplxmul_r(uint32_t a, uint32_t b, uint32_t c) {
return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
}

uint32_t test_cplxmul_r_negative(uint32_t a, uint32_t b, uint32_t c) {
return __builtin_riscv_cv_simd_cplxmul_r(a, b, c, -1); // expected-error {{argument value 255 is outside the valid range [0, 3]}}
}

uint32_t test_cplxmul_i(uint32_t a, uint32_t b, uint32_t c) {
return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
}

uint32_t test_cplxmul_i_negative(uint32_t a, uint32_t b, uint32_t c) {
return __builtin_riscv_cv_simd_cplxmul_i(a, b, c, -1); // expected-error {{argument value 255 is outside the valid range [0, 3]}}
}

uint32_t test_subrotmj(uint32_t a, uint32_t b) {
return __builtin_riscv_cv_simd_subrotmj(a, b, 4); // expected-error {{argument value 4 is outside the valid range [0, 3]}}
}

uint32_t test_subrotmj_negative(uint32_t a, uint32_t b) {
return __builtin_riscv_cv_simd_subrotmj(a, b, -1); // expected-error {{argument value 255 is outside the valid range [0, 3]}}
}
40 changes: 32 additions & 8 deletions clang/test/CodeGen/RISCV/corev-intrinsics/simd.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2430,28 +2430,52 @@ uint32_t test_shuffle_b(uint32_t a, uint32_t b) {
return __builtin_riscv_cv_simd_shuffle_b(a, b);
}

// CHECK-LABEL: @test_shuffle_sci_h(
// CHECK-LABEL: @test_shuffle_sci_h0(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.shuffle.sci.h(i32 [[TMP0]], i32 5)
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.shuffle.sci.h(i32 [[TMP0]], i32 0)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_shuffle_sci_h(uint32_t a) {
return __builtin_riscv_cv_simd_shuffle_sci_h(a, 5);
uint32_t test_shuffle_sci_h0(uint32_t a) {
return __builtin_riscv_cv_simd_shuffle_sci_h(a, 0);
}

// CHECK-LABEL: @test_shuffle_sci_h_negative(
// CHECK-LABEL: @test_shuffle_sci_h1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.shuffle.sci.h(i32 [[TMP0]], i32 -32)
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.shuffle.sci.h(i32 [[TMP0]], i32 1)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_shuffle_sci_h_negative(uint32_t a) {
return __builtin_riscv_cv_simd_shuffle_sci_h(a, -32);
uint32_t test_shuffle_sci_h1(uint32_t a) {
return __builtin_riscv_cv_simd_shuffle_sci_h(a, 1);
}

// CHECK-LABEL: @test_shuffle_sci_h2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.shuffle.sci.h(i32 [[TMP0]], i32 2)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_shuffle_sci_h2(uint32_t a) {
return __builtin_riscv_cv_simd_shuffle_sci_h(a, 2);
}

// CHECK-LABEL: @test_shuffle_sci_h3(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.shuffle.sci.h(i32 [[TMP0]], i32 3)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_shuffle_sci_h3(uint32_t a) {
return __builtin_riscv_cv_simd_shuffle_sci_h(a, 3);
}

// CHECK-LABEL: @test_shuffleI0_sci_b(
Expand Down