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[hmac,dv] Fix fifo_empty interrupt #25683
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martin-velay
commented
Dec 17, 2024
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- linked to issue [hmac,dv] intr_state TB issue #24691
- where the interrupt state for fifo_empty field from the RAL against the RTL were not matching. This was the case when all the empty conditions were filled but at the same time a full is coming. It was just a matter of changing the condition order in the TB.
- fix also FIFO depth status by allowing +1 of tolerance as this is not super critical to be cycle accurate.
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vogelpi
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Dec 21, 2024
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This looks good to me, thanks @martin-velay !
@rswarbrick, any feedback? |
rswarbrick
reviewed
Jan 8, 2025
- linked to issue lowRISC#24691 - where the interrupt state for fifo_empty field from the RAL against the RTL were not matching. This was the case when all the empty conditions were filled but at the same time a full is coming. It was just a matter of changing the condition order in the TB. - fix also FIFO depth status by allowing +1 of tolerance as this is not super critical to be cycle accurate. Signed-off-by: Martin Velay <[email protected]>
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rswarbrick
approved these changes
Jan 10, 2025
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