[top_englishbreakfast] Convert to full topgen flow

Signed-off-by: Alexander Williams <[email protected]>

.gitignore

@@ -64,13 +64,6 @@ hw/foundry/
 # ROM_EXT signer vendored in dependencies
 sw/host/rom_ext_image_signer/vendored_dependencies
 
-# Autogen files for non-Earlgrey tops
-hw/top_englishbreakfast/**/autogen/
-hw/top_englishbreakfast/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
-hw/top_englishbreakfast/ip/sensor_ctrl/rtl/*
-hw/top_englishbreakfast/ip/xbar_main/xbar_main.core
-hw/top_englishbreakfast/ip/xbar_peri/xbar_peri.core
-
 # Rust Cargo build system files.
 sw/host/**/target
 rust-project.json

ci/scripts/build-bitstream-vivado.sh

@@ -26,12 +26,10 @@ case x"$TOPLEVEL" in
     xtop_earlgrey)
         HAS_SCRAMBLED_ROM=1
         HAS_OTP=1
-        RUN_TOPGEN_FUSESOC=0
         ;;
     xtop_englishbreakfast)
         HAS_SCRAMBLED_ROM=0
         HAS_OTP=0
-        RUN_TOPGEN_FUSESOC=1
         ;;
     *)
         usage "Unknown toplevel: $TOPLEVEL"
@@ -86,17 +84,10 @@ else
     OTP_ARG=""
 fi
 
-if [ $RUN_TOPGEN_FUSESOC == 1 ]; then
-    util/topgen-fusesoc.py --files-root=. --topname="$TOPLEVEL"
-    FILESET=topgen
-else
-    FILESET=top
-fi
-
 CORE_NAME="lowrisc:systems:chip_${FLAVOUR}_${TARGET}"
 
 fusesoc --verbose --cores-root=. \
-  run --flag=fileset_$FILESET --target=synth --setup --build \
+  run --target=synth --setup --build \
   --build-root="$OBJ_DIR/hw" \
   "$CORE_NAME" \
   --BootRomInitFile="$BOOTROM_VMEM" \

ci/scripts/build-chip-verilator.sh

@@ -29,7 +29,6 @@ case "$tl" in
         # Englishbreakfast on CI runs on a 2-core CPU
         verilator_options="--threads 2"
         make_options="-j 2"
-        util/topgen-fusesoc.py --files-root=. --topname=top_englishbreakfast
         ;;
     *)
         echo >&2 "Unknown toplevel: $tl"

hw/Makefile

@@ -46,7 +46,7 @@ IPS ?= aes           \
        uart          \
        usbdev
 
-TOPS ?= top_darjeeling top_earlgrey
+TOPS ?= top_darjeeling top_earlgrey top_englishbreakfast
 
 USE_BUFFER ?= 0
 

hw/top_englishbreakfast/chip_englishbreakfast_cw305.core

@@ -10,9 +10,10 @@ filesets:
     depend:
       - lowrisc:prim_xilinx:prim_xilinx_default_pkg
       - lowrisc:systems:top_englishbreakfast:0.1
+      - lowrisc:systems:top_englishbreakfast_pkg
       - lowrisc:systems:top_earlgrey_ast
-      - lowrisc:systems:topgen
       - lowrisc:systems:top_earlgrey_padring
+      - lowrisc:systems:top_earlgrey_scan_role_pkg
     file_type: systemVerilogSource
 
   files_constraints:

hw/top_englishbreakfast/chip_englishbreakfast_verilator.core

@@ -8,7 +8,6 @@ filesets:
   files_sim_verilator:
     depend:
       - lowrisc:systems:top_englishbreakfast:0.1
-      - lowrisc:systems:topgen
       - lowrisc:dv_dpi_c:uartdpi
       - lowrisc:dv_dpi_sv:uartdpi
       - lowrisc:dv_dpi_c:gpiodpi