[topgen] Generate top-specific tests in their outdirs

Darjeeling's software tests only avoided overwriting the earlgrey tests by nature of sorting earlier alphabetically. Move autogenerated tests to the top-specific output directories. Fix up paths to match. Signed-off-by: Alexander Williams <[email protected]>
lowRISC · Dec 27, 2024 · ff3387f · ff3387f
1 parent ec1f8ad
commit ff3387f
Show file tree

Hide file tree

Showing 9 changed files with 33 additions and 34 deletions.
diff --git a/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson b/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson
@@ -23,7 +23,7 @@
       si_stage: SV3
       lc_states: ["PROD"]
       tests: ["chip_sw_alert_test"]
-      bazel: ["//sw/device/tests/autogen:alert_test"]
+      bazel: ["//hw/top_earlgrey/sw/autogen/tests:alert_test"]
     }
     {
       name: chip_sw_alert_handler_escalations
@@ -125,9 +125,9 @@
       lc_states: ["PROD"]
       tests: ["chip_plic_all_irqs_0", "chip_plic_all_irqs_10", "chip_plic_all_irqs_20"]
       bazel: [
-        "//sw/device/tests/autogen:plic_all_irqs_test_0",
-        "//sw/device/tests/autogen:plic_all_irqs_test_10",
-        "//sw/device/tests/autogen:plic_all_irqs_test_20",
+        "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_0",
+        "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_10",
+        "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_20",
       ]
     }
     {

diff --git a/hw/top_earlgrey/data/ip/chip_rv_plic_testplan.hjson b/hw/top_earlgrey/data/ip/chip_rv_plic_testplan.hjson
@@ -26,9 +26,9 @@
         "chip_plic_all_irqs_20",
       ]
       bazel: [
-        "//sw/device/tests/autogen:plic_all_irqs_test_0",
-        "//sw/device/tests/autogen:plic_all_irqs_test_10",
-        "//sw/device/tests/autogen:plic_all_irqs_test_20",
+        "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_0",
+        "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_10",
+        "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_20",
       ]
     }
     {

diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -1302,7 +1302,7 @@
     {
       name: chip_sw_alert_test
       uvm_test_seq: chip_sw_base_vseq
-      sw_images: ["//sw/device/tests/autogen:alert_test:1:new_rules"]
+      sw_images: ["//hw/top_earlgrey/sw/autogen/tests:alert_test:1:new_rules"]
       en_run_modes: ["sw_test_mode_test_rom"]
     }
     {
@@ -1718,19 +1718,19 @@
     {
       name: chip_plic_all_irqs_0
       uvm_test_seq: chip_sw_base_vseq
-      sw_images: ["//sw/device/tests/autogen:plic_all_irqs_test_0:1:new_rules"]
+      sw_images: ["//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_0:1:new_rules"]
       en_run_modes: ["sw_test_mode_test_rom"]
     }
     {
       name: chip_plic_all_irqs_10
       uvm_test_seq: chip_sw_base_vseq
-      sw_images: ["//sw/device/tests/autogen:plic_all_irqs_test_10:1:new_rules"]
+      sw_images: ["//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_10:1:new_rules"]
       en_run_modes: ["sw_test_mode_test_rom"]
     }
     {
       name: chip_plic_all_irqs_20
       uvm_test_seq: chip_sw_base_vseq
-      sw_images: ["//sw/device/tests/autogen:plic_all_irqs_test_20:1:new_rules"]
+      sw_images: ["//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_20:1:new_rules"]
       en_run_modes: ["sw_test_mode_test_rom"]
     }
     {

diff --git a/sw/device/tests/autogen/BUILD → hw/top_earlgrey/sw/autogen/tests/BUILD b/sw/device/tests/autogen/BUILD → hw/top_earlgrey/sw/autogen/tests/BUILD
diff --git a/sw/device/tests/autogen/alert_test.c → ...op_earlgrey/sw/autogen/tests/alert_test.c b/sw/device/tests/autogen/alert_test.c → ...op_earlgrey/sw/autogen/tests/alert_test.c
diff --git a/sw/device/tests/autogen/plic_all_irqs_test.c → ...rey/sw/autogen/tests/plic_all_irqs_test.c b/sw/device/tests/autogen/plic_all_irqs_test.c → ...rey/sw/autogen/tests/plic_all_irqs_test.c
diff --git a/sw/device/tests/sival/BUILD b/sw/device/tests/sival/BUILD
@@ -19,6 +19,9 @@ test_suite(
 test_suite(
     name = "sv2_tests",
     tests = [
+        "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_0",
+        "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_10",
+        "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_20",
         "//sw/device/silicon_creator/lib:otbn_boot_services_functest",
         "//sw/device/tests:aes_smoketest",
         "//sw/device/tests:aon_timer_irq_test",
@@ -63,9 +66,6 @@ test_suite(
         "//sw/device/tests:sram_ctrl_smoketest",
         "//sw/device/tests:uart_smoketest",
         "//sw/device/tests:uart_tx_rx_test",
-        "//sw/device/tests/autogen:plic_all_irqs_test_0",
-        "//sw/device/tests/autogen:plic_all_irqs_test_10",
-        "//sw/device/tests/autogen:plic_all_irqs_test_20",
         "//sw/device/tests/crypto:aes_kwp_functest",
         "//sw/device/tests/crypto:aes_kwp_kat_functest",
         "//sw/device/tests/crypto:ecdh_p256_sideload_functest",
@@ -78,6 +78,8 @@ test_suite(
 test_suite(
     name = "sv3_tests",
     tests = [
+        "//hw/top_earlgrey/sw/autogen/tests:alert_test",
+        "//hw/top_earlgrey/sw/autogen/tests:plic_all_irqs_test_0",
         "//sw/device/silicon_creator/rom/e2e:rom_e2e_smoke",
         "//sw/device/tests:aes_entropy_test",
         "//sw/device/tests:aes_idle_test",
@@ -208,8 +210,6 @@ test_suite(
         "//sw/device/tests:usbdev_stream_test",
         "//sw/device/tests:usbdev_test",
         "//sw/device/tests:usbdev_vbus_test",
-        "//sw/device/tests/autogen:alert_test",
-        "//sw/device/tests/autogen:plic_all_irqs_test_0",
         "//sw/device/tests/crypto:aes_functest",
         "//sw/device/tests/crypto:aes_kwp_sideload_functest",
         "//sw/device/tests/crypto:aes_sideload_functest",

diff --git a/util/topgen.py b/util/topgen.py
@@ -1358,6 +1358,22 @@ def render_template(template_path: str, rendered_path: Path,
                             helper=c_helper,
                             gencmd=gencmd_bzl)
 
+            # Auto-generate tests in "sw/device/tests/autogen" area.
+            for fname in ["plic_all_irqs_test.c", "BUILD"]:
+                outfile = cformat_dir / "tests" / fname
+                render_template(TOPGEN_TEMPLATE_PATH / f"{fname}.tpl",
+                                outfile,
+                                helper=c_helper,
+                                gencmd=gencmd_c)
+
+            # Render alert tests only if there is really an alert handler
+            if lib.find_module(completecfg['module'], 'alert_handler'):
+                outfile = cformat_dir / "tests" / "alert_test.c"
+                render_template(TOPGEN_TEMPLATE_PATH / "alert_test.c.tpl",
+                                outfile,
+                                helper=c_helper,
+                                gencmd=gencmd_c)
+
         # generate chip level xbar and alert_handler TB
         tb_files = [
             "xbar_env_pkg__params.sv", "tb__xbar_connect.sv",
@@ -1395,23 +1411,6 @@ def render_template(template_path: str, rendered_path: Path,
         # generate documentation for toplevel
         gen_top_docs(completecfg, c_helper, out_path)
 
-        # Auto-generate tests in "sw/device/tests/autogen" area.
-        gencmd = warnhdr + GENCMD.format(top_name=top_name)
-        for fname in ["plic_all_irqs_test.c", "BUILD"]:
-            outfile = SRCTREE_TOP / "sw/device/tests/autogen" / fname
-            render_template(TOPGEN_TEMPLATE_PATH / f"{fname}.tpl",
-                            outfile,
-                            helper=c_helper,
-                            gencmd=gencmd)
-
-        # Render alert tests only if there is really an alert handler
-        if lib.find_module(completecfg['module'], 'alert_handler'):
-            outfile = SRCTREE_TOP / "sw/device/tests/autogen" / "alert_test.c"
-            render_template(TOPGEN_TEMPLATE_PATH / "alert_test.c.tpl",
-                            outfile,
-                            helper=c_helper,
-                            gencmd=gencmd)
-
 
 if __name__ == "__main__":
     main()
diff --git a/util/topgen/templates/toplevel.c.tpl b/util/topgen/templates/toplevel.c.tpl
@@ -26,4 +26,4 @@ ${helper.alert_mapping.render_definition()}
  * This array is a mapping from `${helper.plic_interrupts.name.as_c_type()}` to
  * `${helper.plic_sources.name.as_c_type()}`.
  */
-${helper.plic_mapping.render_definition()}
+${helper.plic_mapping.render_definition()}\