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[racl,reggen] reg_top.sv.tpl: Fix _re signals to depend on racl_addr_… #6384

[racl,reggen] reg_top.sv.tpl: Fix _re signals to depend on racl_addr_…

[racl,reggen] reg_top.sv.tpl: Fix _re signals to depend on racl_addr_… #6384

Triggered via push February 21, 2025 08:05
Status Success
Total duration 3h 8m 50s
Artifacts 31

ci.yml

on: push
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1h 9m
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
1h 32m
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310  /  Build bitstream
1h 8m
Earl Grey for CW310 / Build bitstream
Lint (slow)
12m 1s
Lint (slow)
Build documentation
7m 57s
Build documentation
Airgapped build
14m 56s
Airgapped build
Verible lint
0s
Verible lint
Run OTBN smoke Test
3m 54s
Run OTBN smoke Test
Run OTBN crypto tests
3m 6s
Run OTBN crypto tests
Verilated English Breakfast
8m 51s
Verilated English Breakfast
Verilated Earl Grey
1h 16m
Verilated Earl Grey
CW305's Bitstream
26m 14s
CW305's Bitstream
Build Docker Containers
6m 2s
Build Docker Containers
Build and test software
18m 22s
Build and test software
Build and test Darjeeling software
3m 56s
Build and test Darjeeling software
QEMU smoketest
2m 43s
QEMU smoketest
Hyper310 ROM_EXT Tests  /  FPGA test
12m 53s
Hyper310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
24m 36s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
36m 48s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
29m 56s
CW310 Manufacturing Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
4m 29s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
1m 16s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
6m 29s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
16m 32s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
4m 26s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
39m 33s
CW340 Manufacturing Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
6m 1s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
43m 4s
CW310 ROM Tests / FPGA test
Cache bitstreams to GCP
3m 22s
Cache bitstreams to GCP
Verify FPGA jobs
21s
Verify FPGA jobs
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3 errors
Verilated English Breakfast
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.38 MB
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
58.8 KB
execute_manuf_fpga_tests_cw340-targets
594 Bytes
execute_manuf_fpga_tests_cw340-test-results
56.8 KB
execute_rom_ext_fpga_tests_cw310-targets
598 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
31.6 KB
execute_rom_ext_fpga_tests_cw340-targets
427 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
7.03 KB
execute_rom_fpga_tests_cw310-targets
1.73 KB
execute_rom_fpga_tests_cw310-test-results
46.2 KB
execute_rom_fpga_tests_cw340-targets
162 Bytes
execute_rom_fpga_tests_cw340-test-results
201 Bytes
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
37.9 KB
execute_sival_fpga_tests_cw340-targets
514 Bytes
execute_sival_fpga_tests_cw340-test-results
41.1 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.27 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
187 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
449 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
19.9 KB
execute_test_rom_fpga_tests_cw310-targets
326 Bytes
execute_test_rom_fpga_tests_cw310-test-results
3.22 KB
execute_test_rom_fpga_tests_cw340-targets
258 Bytes
execute_test_rom_fpga_tests_cw340-test-results
45 KB
partial-build-bin-chip_earlgrey_cw310
5.99 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
5.99 MB
partial-build-bin-chip_earlgrey_cw340
10 MB
sw_build_test-test-results
73.8 KB
verilated_englishbreakfast
7.02 MB
verilator_earlgrey-test-results
9.19 KB