[racl,reggen] reg_top.sv.tpl: Fix _re signals to depend on racl_addr_…

…hit_read

...  instead of racl_addr_hit_write.

With the introduction of RACL the _re and _we signals in reg_enable_gen were changed from
addr_hit to wr_addr_hit, which depends on racl_addr_hit_write.
However, _we should use racl_addr_hit_read instead.

Signed-off-by: David Schrammel <[email protected]>

hw/ip/gpio/rtl/gpio_reg_top.sv

@@ -813,33 +813,33 @@ module gpio_reg_top
   assign alert_test_we = racl_addr_hit_write[3] & reg_we & !reg_error;
 
   assign alert_test_wd = reg_wdata[0];
-  assign direct_out_re = racl_addr_hit_write[5] & reg_re & !reg_error;
+  assign direct_out_re = racl_addr_hit_read[5] & reg_re & !reg_error;
   assign direct_out_we = racl_addr_hit_write[5] & reg_we & !reg_error;
 
   assign direct_out_wd = reg_wdata[31:0];
-  assign masked_out_lower_re = racl_addr_hit_write[6] & reg_re & !reg_error;
+  assign masked_out_lower_re = racl_addr_hit_read[6] & reg_re & !reg_error;
   assign masked_out_lower_we = racl_addr_hit_write[6] & reg_we & !reg_error;
 
   assign masked_out_lower_data_wd = reg_wdata[15:0];
 
   assign masked_out_lower_mask_wd = reg_wdata[31:16];
-  assign masked_out_upper_re = racl_addr_hit_write[7] & reg_re & !reg_error;
+  assign masked_out_upper_re = racl_addr_hit_read[7] & reg_re & !reg_error;
   assign masked_out_upper_we = racl_addr_hit_write[7] & reg_we & !reg_error;
 
   assign masked_out_upper_data_wd = reg_wdata[15:0];
 
   assign masked_out_upper_mask_wd = reg_wdata[31:16];
-  assign direct_oe_re = racl_addr_hit_write[8] & reg_re & !reg_error;
+  assign direct_oe_re = racl_addr_hit_read[8] & reg_re & !reg_error;
   assign direct_oe_we = racl_addr_hit_write[8] & reg_we & !reg_error;
 
   assign direct_oe_wd = reg_wdata[31:0];
-  assign masked_oe_lower_re = racl_addr_hit_write[9] & reg_re & !reg_error;
+  assign masked_oe_lower_re = racl_addr_hit_read[9] & reg_re & !reg_error;
   assign masked_oe_lower_we = racl_addr_hit_write[9] & reg_we & !reg_error;
 
   assign masked_oe_lower_data_wd = reg_wdata[15:0];
 
   assign masked_oe_lower_mask_wd = reg_wdata[31:16];
-  assign masked_oe_upper_re = racl_addr_hit_write[10] & reg_re & !reg_error;
+  assign masked_oe_upper_re = racl_addr_hit_read[10] & reg_re & !reg_error;
   assign masked_oe_upper_we = racl_addr_hit_write[10] & reg_we & !reg_error;
 
   assign masked_oe_upper_data_wd = reg_wdata[15:0];

hw/ip/i2c/rtl/i2c_reg_top.sv

@@ -3620,8 +3620,8 @@ module i2c_reg_top
   assign ctrl_multi_controller_monitor_en_wd = reg_wdata[5];
 
   assign ctrl_tx_stretch_ctrl_en_wd = reg_wdata[6];
-  assign status_re = racl_addr_hit_write[5] & reg_re & !reg_error;
-  assign rdata_re = racl_addr_hit_write[6] & reg_re & !reg_error;
+  assign status_re = racl_addr_hit_read[5] & reg_re & !reg_error;
+  assign rdata_re = racl_addr_hit_read[6] & reg_re & !reg_error;
   assign fdata_we = racl_addr_hit_write[7] & reg_we & !reg_error;
 
   assign fdata_fbyte_wd = reg_wdata[7:0];
@@ -3654,16 +3654,16 @@ module i2c_reg_top
   assign target_fifo_config_tx_thresh_wd = reg_wdata[11:0];
 
   assign target_fifo_config_acq_thresh_wd = reg_wdata[27:16];
-  assign host_fifo_status_re = racl_addr_hit_write[11] & reg_re & !reg_error;
-  assign target_fifo_status_re = racl_addr_hit_write[12] & reg_re & !reg_error;
+  assign host_fifo_status_re = racl_addr_hit_read[11] & reg_re & !reg_error;
+  assign target_fifo_status_re = racl_addr_hit_read[12] & reg_re & !reg_error;
   assign ovrd_we = racl_addr_hit_write[13] & reg_we & !reg_error;
 
   assign ovrd_txovrden_wd = reg_wdata[0];
 
   assign ovrd_sclval_wd = reg_wdata[1];
 
   assign ovrd_sdaval_wd = reg_wdata[2];
-  assign val_re = racl_addr_hit_write[14] & reg_re & !reg_error;
+  assign val_re = racl_addr_hit_read[14] & reg_re & !reg_error;
   assign timing0_we = racl_addr_hit_write[15] & reg_we & !reg_error;
 
   assign timing0_thigh_wd = reg_wdata[12:0];
@@ -3705,7 +3705,7 @@ module i2c_reg_top
   assign target_id_address1_wd = reg_wdata[20:14];
 
   assign target_id_mask1_wd = reg_wdata[27:21];
-  assign acqdata_re = racl_addr_hit_write[22] & reg_re & !reg_error;
+  assign acqdata_re = racl_addr_hit_read[22] & reg_re & !reg_error;
   assign txdata_we = racl_addr_hit_write[23] & reg_we & !reg_error;
 
   assign txdata_wd = reg_wdata[7:0];
@@ -3717,16 +3717,16 @@ module i2c_reg_top
   assign target_timeout_ctrl_val_wd = reg_wdata[30:0];
 
   assign target_timeout_ctrl_en_wd = reg_wdata[31];
-  assign target_nack_count_re = racl_addr_hit_write[26] & reg_re & !reg_error;
+  assign target_nack_count_re = racl_addr_hit_read[26] & reg_re & !reg_error;
 
   assign target_nack_count_wd = '1;
-  assign target_ack_ctrl_re = racl_addr_hit_write[27] & reg_re & !reg_error;
+  assign target_ack_ctrl_re = racl_addr_hit_read[27] & reg_re & !reg_error;
   assign target_ack_ctrl_we = racl_addr_hit_write[27] & reg_we & !reg_error;
 
   assign target_ack_ctrl_nbytes_wd = reg_wdata[8:0];
 
   assign target_ack_ctrl_nack_wd = reg_wdata[31];
-  assign acq_fifo_next_data_re = racl_addr_hit_write[28] & reg_re & !reg_error;
+  assign acq_fifo_next_data_re = racl_addr_hit_read[28] & reg_re & !reg_error;
   assign host_nack_handler_timeout_we = racl_addr_hit_write[29] & reg_we & !reg_error;
 
   assign host_nack_handler_timeout_val_wd = reg_wdata[30:0];

hw/ip/mbx/rtl/mbx_soc_reg_top.sv

@@ -542,7 +542,7 @@ module mbx_soc_reg_top
   end
 
   // Generate write-enables
-  assign soc_control_re = racl_addr_hit_write[0] & reg_re & !reg_error;
+  assign soc_control_re = racl_addr_hit_read[0] & reg_re & !reg_error;
   assign soc_control_we = racl_addr_hit_write[0] & reg_we & !reg_error;
 
   assign soc_control_abort_wd = reg_wdata[0];

hw/ip/spi_device/rtl/spi_device_reg_top.sv

@@ -19746,7 +19746,7 @@ module spi_device_reg_top
   assign cfg_rx_order_wd = reg_wdata[3];
 
   assign cfg_mailbox_en_wd = reg_wdata[24];
-  assign status_re = racl_addr_hit_write[6] & reg_re & !reg_error;
+  assign status_re = racl_addr_hit_read[6] & reg_re & !reg_error;
   assign intercept_en_we = racl_addr_hit_write[7] & reg_we & !reg_error;
 
   assign intercept_en_status_wd = reg_wdata[0];
@@ -19756,12 +19756,12 @@ module spi_device_reg_top
   assign intercept_en_sfdp_wd = reg_wdata[2];
 
   assign intercept_en_mbx_wd = reg_wdata[3];
-  assign addr_mode_re = racl_addr_hit_write[8] & reg_re & !reg_error;
+  assign addr_mode_re = racl_addr_hit_read[8] & reg_re & !reg_error;
   assign addr_mode_we = racl_addr_hit_write[8] & reg_we & !reg_error;
 
   assign addr_mode_addr_4b_en_wd = reg_wdata[0];
-  assign last_read_addr_re = racl_addr_hit_write[9] & reg_re & !reg_error;
-  assign flash_status_re = racl_addr_hit_write[10] & reg_re & !reg_error;
+  assign last_read_addr_re = racl_addr_hit_read[9] & reg_re & !reg_error;
+  assign flash_status_re = racl_addr_hit_read[10] & reg_re & !reg_error;
   assign flash_status_we = racl_addr_hit_write[10] & reg_we & !reg_error;
 
   assign flash_status_busy_wd = reg_wdata[0];
@@ -19785,8 +19785,8 @@ module spi_device_reg_top
   assign mailbox_addr_we = racl_addr_hit_write[14] & reg_we & !reg_error;
 
   assign mailbox_addr_wd = reg_wdata[31:0];
-  assign upload_cmdfifo_re = racl_addr_hit_write[17] & reg_re & !reg_error;
-  assign upload_addrfifo_re = racl_addr_hit_write[18] & reg_re & !reg_error;
+  assign upload_cmdfifo_re = racl_addr_hit_read[17] & reg_re & !reg_error;
+  assign upload_addrfifo_re = racl_addr_hit_read[18] & reg_re & !reg_error;
   assign cmd_filter_0_we = racl_addr_hit_write[19] & reg_we & !reg_error;
 
   assign cmd_filter_0_filter_0_wd = reg_wdata[0];
@@ -20998,7 +20998,7 @@ module spi_device_reg_top
   assign tpm_cfg_tpm_reg_chk_dis_wd = reg_wdata[3];
 
   assign tpm_cfg_invalid_locality_wd = reg_wdata[4];
-  assign tpm_status_re = racl_addr_hit_write[61] & reg_re & !reg_error;
+  assign tpm_status_re = racl_addr_hit_read[61] & reg_re & !reg_error;
   assign tpm_status_we = racl_addr_hit_write[61] & reg_we & !reg_error;
 
   assign tpm_status_wrfifo_pending_wd = reg_wdata[1];
@@ -21037,7 +21037,7 @@ module spi_device_reg_top
   assign tpm_rid_we = racl_addr_hit_write[70] & reg_we & !reg_error;
 
   assign tpm_rid_wd = reg_wdata[7:0];
-  assign tpm_cmd_addr_re = racl_addr_hit_write[71] & reg_re & !reg_error;
+  assign tpm_cmd_addr_re = racl_addr_hit_read[71] & reg_re & !reg_error;
   assign tpm_read_fifo_we = racl_addr_hit_write[72] & reg_we & !reg_error;
 
   assign tpm_read_fifo_wd = reg_wdata[31:0];

hw/ip/uart/rtl/uart_reg_top.sv

@@ -1734,8 +1734,8 @@ module uart_reg_top
   assign ctrl_rxblvl_wd = reg_wdata[9:8];
 
   assign ctrl_nco_wd = reg_wdata[31:16];
-  assign status_re = racl_addr_hit_write[5] & reg_re & !reg_error;
-  assign rdata_re = racl_addr_hit_write[6] & reg_re & !reg_error;
+  assign status_re = racl_addr_hit_read[5] & reg_re & !reg_error;
+  assign rdata_re = racl_addr_hit_read[6] & reg_re & !reg_error;
   assign wdata_we = racl_addr_hit_write[7] & reg_we & !reg_error;
 
   assign wdata_wd = reg_wdata[7:0];
@@ -1748,13 +1748,13 @@ module uart_reg_top
   assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2];
 
   assign fifo_ctrl_txilvl_wd = reg_wdata[7:5];
-  assign fifo_status_re = racl_addr_hit_write[9] & reg_re & !reg_error;
+  assign fifo_status_re = racl_addr_hit_read[9] & reg_re & !reg_error;
   assign ovrd_we = racl_addr_hit_write[10] & reg_we & !reg_error;
 
   assign ovrd_txen_wd = reg_wdata[0];
 
   assign ovrd_txval_wd = reg_wdata[1];
-  assign val_re = racl_addr_hit_write[11] & reg_re & !reg_error;
+  assign val_re = racl_addr_hit_read[11] & reg_re & !reg_error;
   assign timeout_ctrl_we = racl_addr_hit_write[12] & reg_we & !reg_error;
 
   assign timeout_ctrl_val_wd = reg_wdata[23:0];