[prim,ipgen] Fix up some hierarchies of fusesoc cores #3629

Job	Run time
Lint (quick)	3m 23s
Lint (slow)	11m 22s
Build Docker Containers	2m 36s
Build documentation	5m 50s
Airgapped build	7m 36s
CW305's Bitstream	15m 39s
Run OTBN crypto tests	20m 7s
Build and test software	17m 25s
Run OTBN smoke Test	2m 44s
Verilated Earl Grey	1h 27m 14s
Verible lint	59s
Verilated English Breakfast	8m 5s
Earl Grey for CW310 / Build bitstream	1h 5m 53s
Earl Grey for CW310 Hyperdebug / Build bitstream	1h 10m 4s
Earl Grey for CW340 / Build bitstream	1h 24m 56s
CW310 Test ROM Tests / FPGA test	3m 54s
CW310 ROM_EXT Tests / FPGA test	4m 47s
CW310 ROM Tests / FPGA test	43m 18s
CW310 Manufacturing Tests / FPGA test	29m 29s
CW310 SiVal ROM_EXT Tests / FPGA test	33m 9s
CW310 SiVal Tests / FPGA test	25m 42s
Cache bitstreams to GCP	0s
CW340 ROM_EXT Tests / FPGA test	5m 55s
CW340 Manufacturing Tests / FPGA test	6m 50s
CW340 ROM Tests / FPGA test	48s
CW340 Test ROM Tests / FPGA test	3m 20s
CW340 SiVal Tests / FPGA test	17m 17s
CW340 SiVal ROM_EXT Tests / FPGA test	3m 49s
Verify FPGA jobs	38s
	9h 42m 49s

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