Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Push result from FUs #792

Merged
merged 8 commits into from
Jan 25, 2025
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 3 additions & 3 deletions coreblocks/func_blocks/csr/csr.py
Original file line number Diff line number Diff line change
Expand Up @@ -57,8 +57,8 @@ class CSRUnit(FuncBlock, Elaboratable):
update: Method
Method from standard RS interface. Receives announcements of computed register values.
get_result: Method
`accept` method from standard FU interface. Used to receive instruction result and pass it
to the next pipeline stage.
Method from standard RS func block interface. Used to receive instruction result and pass
it to the next pipeline stage.
"""

def __init__(self, gen_params: GenParams):
Expand All @@ -79,7 +79,7 @@ def __init__(self, gen_params: GenParams):
self.select = Method(o=self.csr_layouts.rs.select_out)
self.insert = Method(i=self.csr_layouts.rs.insert_in)
self.update = Method(i=self.csr_layouts.rs.update_in)
self.get_result = Method(o=self.fu_layouts.accept)
self.get_result = Method(o=self.fu_layouts.push_result)

self.regfile: dict[int, tuple[Method, Method]] = {}

Expand Down
11 changes: 3 additions & 8 deletions coreblocks/func_blocks/fu/alu.py
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,6 @@
from amaranth import *

from transactron import *
from transactron.lib import FIFO
from transactron.lib.metrics import *

from coreblocks.arch import OpType, Funct3, Funct7
Expand Down Expand Up @@ -242,7 +241,7 @@ def __init__(self, gen_params: GenParams, alu_fn=AluFn()):
layouts = gen_params.get(FuncUnitLayouts)

self.issue = Method(i=layouts.issue)
self.accept = Method(o=layouts.accept)
self.push_result = Method(i=layouts.push_result)

self.perf_instr = TaggedCounter(
"backend.fu.alu.instr",
Expand All @@ -256,13 +255,8 @@ def elaborate(self, platform):
m.submodules += [self.perf_instr]

m.submodules.alu = alu = Alu(self.gen_params, alu_fn=self.alu_fn)
m.submodules.fifo = fifo = FIFO(self.gen_params.get(FuncUnitLayouts).accept, 2)
m.submodules.decoder = decoder = self.alu_fn.get_decoder(self.gen_params)

@def_method(m, self.accept)
def _():
return fifo.read(m)

@def_method(m, self.issue)
def _(arg):
m.d.av_comb += decoder.exec_fn.eq(arg.exec_fn)
Expand All @@ -273,14 +267,15 @@ def _(arg):

self.perf_instr.incr(m, decoder.decode_fn)

fifo.write(m, rob_id=arg.rob_id, result=alu.out, rp_dst=arg.rp_dst, exception=0)
self.push_result(m, rob_id=arg.rob_id, result=alu.out, rp_dst=arg.rp_dst, exception=0)

return m


@dataclass(frozen=True)
class ALUComponent(FunctionalComponentParams):
_: KW_ONLY
result_fifo: bool = True
zba_enable: bool = False
zbb_enable: bool = False
zicond_enable: bool = False
Expand Down
23 changes: 16 additions & 7 deletions coreblocks/func_blocks/fu/common/rs_func_block.py
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
from coreblocks.scheduler.wakeup_select import WakeupSelect
from transactron import Method, TModule
from coreblocks.func_blocks.interface.func_protocols import FuncUnit, FuncBlock
from transactron.lib import Collector
from transactron.lib import FIFO, Collector, Connect
from coreblocks.arch import OpType
from coreblocks.interface.layouts import RSLayouts, FuncUnitLayouts

Expand Down Expand Up @@ -34,7 +34,7 @@ class RSFuncBlock(FuncBlock, Elaboratable):
def __init__(
self,
gen_params: GenParams,
func_units: Iterable[tuple[FuncUnit, set[OpType]]],
func_units: Iterable[tuple[FuncUnit, set[OpType], bool]],
rs_entries: int,
rs_number: int,
rs_type: type[RSBase],
Expand Down Expand Up @@ -65,7 +65,7 @@ def __init__(
self.insert = Method(i=self.rs_layouts.rs.insert_in)
self.select = Method(o=self.rs_layouts.rs.select_out)
self.update = Method(i=self.rs_layouts.rs.update_in)
self.get_result = Method(o=self.fu_layouts.accept)
self.get_result = Method(o=self.fu_layouts.push_result)

def elaborate(self, platform):
m = TModule()
Expand All @@ -74,20 +74,29 @@ def elaborate(self, platform):
gen_params=self.gen_params,
rs_entries=self.rs_entries,
rs_number=self.rs_number,
ready_for=(optypes for _, optypes in self.func_units),
ready_for=(optypes for _, optypes, _ in self.func_units),
)

for n, (func_unit, _) in enumerate(self.func_units):
targets: list[Method] = []

for n, (func_unit, _, result_fifo) in enumerate(self.func_units):
wakeup_select = WakeupSelect(
gen_params=self.gen_params,
get_ready=self.rs.get_ready_list[n],
take_row=self.rs.take,
issue=func_unit.issue,
)
if result_fifo:
connector = FIFO(self.gen_params.get(FuncUnitLayouts).push_result, 2)
else:
connector = Connect(self.gen_params.get(FuncUnitLayouts).push_result)
m.submodules[f"func_unit_{n}"] = func_unit
m.submodules[f"wakeup_select_{n}"] = wakeup_select
m.submodules[f"connector_{n}"] = connector
func_unit.push_result.proxy(m, connector.write)
targets.append(connector.read)

m.submodules.collector = collector = Collector([func_unit.accept for func_unit, _ in self.func_units])
m.submodules.collector = collector = Collector(targets)

self.insert.proxy(m, self.rs.insert)
self.select.proxy(m, self.rs.select)
Expand All @@ -105,7 +114,7 @@ class RSBlockComponent(BlockComponentParams):
rs_type: type[RSBase] = RS

def get_module(self, gen_params: GenParams) -> FuncBlock:
modules = list((u.get_module(gen_params), u.get_optypes()) for u in self.func_units)
modules = list((u.get_module(gen_params), u.get_optypes(), u.result_fifo) for u in self.func_units)
rs_unit = RSFuncBlock(
gen_params=gen_params,
func_units=modules,
Expand Down
11 changes: 3 additions & 8 deletions coreblocks/func_blocks/fu/div_unit.py
Original file line number Diff line number Diff line change
Expand Up @@ -48,15 +48,14 @@ def __init__(self, gen_params: GenParams, ipc: int = 4, div_fn=DivFn()):
layouts = gen_params.get(FuncUnitLayouts)

self.issue = Method(i=layouts.issue)
self.accept = Method(o=layouts.accept)
self.push_result = Method(i=layouts.push_result)
self.clear = Method()

self.div_fn = div_fn

def elaborate(self, platform):
m = TModule()

m.submodules.result_fifo = result_fifo = BasicFifo(self.gen_params.get(FuncUnitLayouts).accept, 2)
m.submodules.params_fifo = params_fifo = FIFO(
[
("rob_id", self.gen_params.rob_entries_bits),
Expand All @@ -75,13 +74,8 @@ def elaborate(self, platform):

@def_method(m, self.clear)
def _():
result_fifo.clear(m)
divider.clear(m)

@def_method(m, self.accept)
def _():
return result_fifo.read(m)

@def_method(m, self.issue)
def _(arg):
m.d.av_comb += decoder.exec_fn.eq(arg.exec_fn)
Expand Down Expand Up @@ -132,14 +126,15 @@ def _abs(s: Value) -> Value:
flip_sig = Mux(params.flip_sign, ~result[sign_bit], 0)
sign_result = Mux(flip_sig, -result, result)

result_fifo.write(m, rob_id=params.rob_id, result=sign_result, rp_dst=params.rp_dst, exception=0)
self.push_result(m, rob_id=params.rob_id, result=sign_result, rp_dst=params.rp_dst, exception=0)

return m


@dataclass(frozen=True)
class DivComponent(FunctionalComponentParams):
_: KW_ONLY
result_fifo: bool = False # last step is registered
ipc: int = 3 # iterations per cycle
decoder_manager: DivFn = DivFn()

Expand Down
14 changes: 5 additions & 9 deletions coreblocks/func_blocks/fu/exception.py
Original file line number Diff line number Diff line change
@@ -1,11 +1,10 @@
from dataclasses import dataclass
from dataclasses import dataclass, KW_ONLY
from typing import Sequence
from amaranth import *
from coreblocks.arch.isa_consts import PrivilegeLevel
from transactron.utils.dependencies import DependencyContext

from transactron import *
from transactron.lib import FIFO

from coreblocks.params import GenParams, FunctionalComponentParams
from coreblocks.arch import OpType, Funct3, ExceptionCause
Expand Down Expand Up @@ -50,21 +49,16 @@ def __init__(self, gen_params: GenParams, unit_fn=ExceptionUnitFn()):
layouts = gen_params.get(FuncUnitLayouts)

self.issue = Method(i=layouts.issue)
self.accept = Method(o=layouts.accept)
self.push_result = Method(i=layouts.push_result)

self.dm = DependencyContext.get()
self.report = self.dm.get_dependency(ExceptionReportKey())

def elaborate(self, platform):
m = TModule()

m.submodules.fifo = fifo = FIFO(self.gen_params.get(FuncUnitLayouts).accept, 2)
m.submodules.decoder = decoder = self.fn.get_decoder(self.gen_params)

@def_method(m, self.accept)
def _():
return fifo.read(m)

@def_method(m, self.issue)
def _(arg):
m.d.comb += decoder.exec_fn.eq(arg.exec_fn)
Expand Down Expand Up @@ -104,13 +98,15 @@ def _(arg):

self.report(m, rob_id=arg.rob_id, cause=cause, pc=arg.pc, mtval=mtval)

fifo.write(m, result=0, exception=1, rob_id=arg.rob_id, rp_dst=arg.rp_dst)
self.push_result(m, result=0, exception=1, rob_id=arg.rob_id, rp_dst=arg.rp_dst)

return m


@dataclass(frozen=True)
class ExceptionUnitComponent(FunctionalComponentParams):
_: KW_ONLY
result_fifo: bool = True
decoder_manager: ExceptionUnitFn = ExceptionUnitFn()

def get_module(self, gen_params: GenParams) -> FuncUnit:
Expand Down
18 changes: 9 additions & 9 deletions coreblocks/func_blocks/fu/jumpbranch.py
Original file line number Diff line number Diff line change
Expand Up @@ -134,7 +134,7 @@ def __init__(self, gen_params: GenParams, jb_fn=JumpBranchFn()):
layouts = gen_params.get(FuncUnitLayouts)

self.issue = Method(i=layouts.issue)
self.accept = Method(o=layouts.accept)
self.push_result = Method(i=layouts.push_result)

self.fifo_branch_resolved = FIFO(self.gen_params.get(JumpBranchLayouts).verify_branch, 2)

Expand Down Expand Up @@ -181,8 +181,7 @@ def elaborate(self, platform):
)
m.submodules.instr_fifo = instr_fifo = BasicFifo(instr_fifo_layout, 2)

@def_method(m, self.accept)
def _():
with Transaction().body(m):
instr = instr_fifo.read(m)
target_prediction = jump_target_resp(m)

Expand Down Expand Up @@ -250,12 +249,13 @@ def _():
misprediction,
)

return {
"rob_id": instr.rob_id,
"result": instr.reg_res,
"rp_dst": instr.rp_dst,
"exception": exception,
}
self.push_result(
m,
rob_id=instr.rob_id,
result=instr.reg_res,
rp_dst=instr.rp_dst,
exception=exception,
)

@def_method(m, self.issue)
def _(arg):
Expand Down
18 changes: 9 additions & 9 deletions coreblocks/func_blocks/fu/lsu/dummyLsu.py
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ def __init__(self, gen_params: GenParams, bus: BusMasterInterface) -> None:
self.report = self.dependency_manager.get_dependency(ExceptionReportKey())

self.issue = Method(i=self.fu_layouts.issue)
self.accept = Method(o=self.fu_layouts.accept)
self.push_result = Method(i=self.fu_layouts.push_result)

self.bus = bus

Expand Down Expand Up @@ -121,8 +121,7 @@ def _(arg):
results_noop.write(m, data=0, exception=0, cause=0, addr=0)
issued_noop.write(m, arg)

@def_method(m, self.accept)
def _():
with Transaction().body(m):
arg = Signal(self.fu_layouts.issue)
res = Signal(self.lsu_layouts.accept)
with condition(m) as branch:
Expand All @@ -138,12 +137,13 @@ def _():

self.log.debug(m, 1, "accept rob_id={} result=0x{:08x} exception={}", arg.rob_id, res.data, res.exception)

return {
"rob_id": arg["rob_id"],
"rp_dst": arg["rp_dst"],
"result": res["data"],
"exception": res["exception"],
}
self.push_result(
m,
rob_id=arg["rob_id"],
rp_dst=arg["rp_dst"],
result=res["data"],
exception=res["exception"],
)

with Transaction().body(m):
precommit = self.dependency_manager.get_dependency(InstructionPrecommitKey())
Expand Down
Loading
Loading