Unscheduled DFCIR & SystemVerilog output path options revamp

README.md

@@ -216,13 +216,16 @@ The list of arguments for `hls`-mode is presented below:
 
 * `-h,--help`: *optional* flag; used to print the help-message about other arguments.
 * `--config <PATH>`: *required* filesystem-path option; used to specify the file for a JSON latency configuration file. Its format is presented in *JSON Configuration* section.
-* `--out <NAME>`: *optional* filesystem-path option; used to specify the destination file for the output SystemVerilog to be generated in. If the name isn't provided or the provided name is an empty string, standard output stream is used.
+* `--out-sv <PATH>`: *optional* filesystem-path option; used to specify the output SystemVerilog file.
+* `--out-dfcir <PATH>`: *optional* filesystem-path option; used to specify the output DFCIR file.
 * `-a` or `-l`: *required* flag; used to specify the chosen scheduling strategy - either as-soon-as-possible or linear programming. **Exactly one of these flags has to be specified**.
 
+**At least one of the `out-*` options has to be specified.**
+
 Here is an example of an Utopia HLS CLI call:
 
 ```bash
-umain hls --config ~/utopia-user/config.json --out ~/outFile -a
+umain hls --config ~/utopia-user/config.json --out-sv ~/outFile.sv --out-dfcir ~/outFile2.mlir -a
 ```
 
 ### JSON Configuration
@@ -270,7 +273,7 @@ For example, given subdirectory `polynomial2`, the compilation and execution com
 ```bash
 cmake -S . -B build -G Ninja -DCMAKE_PREFIX_PATH=~/firtool-1.72.0 -DSRC_FILES="~/utopia-hls/examples/polynomial2/polynomial2.cpp"
 cmake --build build
-build/src/umain hls --config examples/polynomial2/polynomial2.json -a
+build/src/umain hls --config examples/polynomial2/polynomial2.json -a --out-sv output
 ```
 
 ## DFCxx Documentation

src/model/dfcxx/include/dfcxx/typedefs.h

@@ -61,6 +61,7 @@ enum Scheduler {
 // Used for accessing specified output format paths.
 enum class OutputFormatID : uint8_t {
   SystemVerilog = 0,
+  DFCIR,
   // Utility value. Constains the number of elements in the enum.
   COUNT
 };

src/model/dfcxx/lib/dfcxx/converter.cpp

@@ -26,6 +26,12 @@ bool DFCIRConverter::convertAndPrint(mlir::ModuleOp module,
                                      const Scheduler &sched) {
   mlir::MLIRContext *context = module.getContext();
   mlir::PassManager pm(context);
+
+  // Dump DFCIR if the corresponding option is specified.
+  if (auto *stream = outputStreams[OUT_FORMAT_ID_INT(DFCIR)]) {
+    module.print(*stream);
+  }
+
   pm.addPass(mlir::dfcir::createDFCIRToFIRRTLPass(&config));
   switch (sched) {
     case Linear:
@@ -35,10 +41,14 @@ bool DFCIRConverter::convertAndPrint(mlir::ModuleOp module,
       pm.addPass(mlir::dfcir::createDFCIRASAPSchedulerPass());
       break;
   }
-  pm.addPass(circt::createLowerFIRRTLToHWPass());
-  pm.addPass(circt::createLowerSeqToSVPass());
-  pm.addPass(circt::createExportVerilogPass(*(
-      outputStreams[OUT_FORMAT_ID_INT(SystemVerilog)])));
+
+  // Add FIRRTL->SystemVerilog passes if SystemVerilog output option is specified.
+  if (auto *stream = outputStreams[OUT_FORMAT_ID_INT(SystemVerilog)]) {
+    pm.addPass(circt::createLowerFIRRTLToHWPass());
+    pm.addPass(circt::createLowerSeqToSVPass());
+    pm.addPass(circt::createExportVerilogPass(*stream));
+  }
+
   auto result = pm.run(module);
   return result.succeeded();
 }

src/options.h

@@ -35,7 +35,8 @@
 #define CONFIG_JSON "config"
 #define ASAP_SCHEDULER_JSON "asap_scheduler"
 #define LP_SCHEDULER_JSON "lp_scheduler"
-#define SV_OUT_JSON "sv_out"
+#define OUT_SV_JSON "out_sv"
+#define OUT_DFCIR_JSON "out_dfcir"
 
 //===----------------------------------------------------------------------===//
 // CLI args/flags definitions
@@ -46,7 +47,8 @@
 #define ASAP_SCHEDULER_FLAG CLI_FLAG("a")
 #define LP_SCHEDULER_FLAG CLI_FLAG("l")
 #define OUTPUT_GROUP "output"
-#define SV_OUT_ARG CLI_ARG("sv_out")
+#define OUT_SV_ARG CLI_ARG("out-sv")
+#define OUT_DFCIR_ARG CLI_ARG("out-dfcir")
 
 //===----------------------------------------------------------------------===//
 
@@ -177,17 +179,21 @@ struct HlsOptions final : public AppOptions {
                          "Use Linear Programming scheduler");
     schedGroup->require_option(1); 
     auto outputGroup = options->add_option_group(OUTPUT_GROUP);
-    outputGroup->add_option(SV_OUT_ARG,
+    outputGroup->add_option(OUT_SV_ARG,
                             outNames[OUT_FORMAT_ID_INT(SystemVerilog)],
-                            "Path to output SystemVerilog module to");
+                            "Path to output the SystemVerilog module");
+    outputGroup->add_option(OUT_DFCIR_ARG,
+                            outNames[OUT_FORMAT_ID_INT(DFCIR)],
+                            "Path to output unscheduled DFCIR");
     outputGroup->require_option();
   }
 
   void fromJson(Json json) override {
     get(json, CONFIG_JSON,         latConfigFile);
     get(json, ASAP_SCHEDULER_JSON, asapScheduler);
     get(json, LP_SCHEDULER_JSON,   lpScheduler);
-    get(json, SV_OUT_JSON,         outNames[OUT_FORMAT_ID_INT(SystemVerilog)]);
+    get(json, OUT_SV_JSON,         outNames[OUT_FORMAT_ID_INT(SystemVerilog)]);
+    get(json, OUT_DFCIR_JSON,      outNames[OUT_FORMAT_ID_INT(DFCIR)]);
   }
 
   std::string latConfigFile;