Release v0.4.1 · intel/rohd

What's Changed

resolves #153 by @akshay-wankhede in #171
resolves issue #138 by @quekyj in #190
Fixes: 157 by @akshay-wankhede in #203
Fix bugs related to module naming and instantiation by @mkorbel1 in #207
Allow constants for modulo and shift operations on Logic by @mkorbel1 in #208
Fix typo on modulo test by @mkorbel1 in #209
_Wires underneath Logics by @mkorbel1 in #199
Fix bugs related to 64-bit int conversion, fix #212 by @mkorbel1 in #213
[Issue-12] simpler constructor of simple control blocks by @quekyj in #210
Replace awkward map+reduce chain with smart literal by @eric-norige in #214
Optimize LogicValue operations to avoid Strings where possible by @mkorbel1 in #215
[Issue-112] Automatically extract rohd version from pubspec to add into generated sv by @quekyj in #200
Fix bug related to late connection signal prop with wires by @mkorbel1 in #218
Fixed LogicValue hash and equality inconsistency by forcing construction consistency by @mkorbel1 in #217
Fix the tree example doc by @mkorbel1 in #222
[Issue-114] Add test to sequential driver on same signal to return Exception by @quekyj in #197

Full Changelog: v0.4.0...v0.4.1