Doc fixes and a couple more tests

.gitignore

@@ -17,6 +17,7 @@ tmp_test/
 *.vcd
 *_fsm.md
 .vscode/*
+devtools_options.yaml
 
 # Exceptions
 !.vscode/extensions.json

.pubignore

@@ -17,6 +17,7 @@ tmp_test/
 *.vcd
 *_fsm.md
 .vscode/*
+devtools_options.yaml
 
 # Exceptions
 !.vscode/extensions.json

doc/user_guide/_docs/A11-interfaces.md

@@ -88,7 +88,7 @@ class SimpleInterface extends PairInterface {
   SimpleInterface()
       : super(
           portsFromConsumer: [Port('rsp')],
-          portsFromProducer: [Port('req')],
+          portsFromProvider: [Port('req')],
           sharedInputPorts: [Port('clk')],
         );
 

lib/src/interfaces/pair_interface.dart

@@ -96,7 +96,7 @@ class PairInterface extends Interface<PairDirection> {
           })
           .toList(growable: false);
 
-  /// Creates a new instance of a [PairInterface] with the same ports other
+  /// Creates a new instance of a [PairInterface] with the same ports and other
   /// characteristics.
   PairInterface.clone(PairInterface otherInterface)
       : this(

test/array_collapsing_test.dart

@@ -11,6 +11,8 @@ import 'package:rohd/rohd.dart';
 import 'package:rohd/src/utilities/simcompare.dart';
 import 'package:test/test.dart';
 
+import 'logic_array_test.dart';
+
 class ArrayModule extends Module {
   ArrayModule(LogicArray a) {
     final inpA = addInputArray('a', a, dimensions: a.dimensions);
@@ -22,6 +24,36 @@ class ArrayModule extends Module {
   }
 }
 
+class ArrayTopMod extends Module {
+  ArrayTopMod(Logic clk) {
+    clk = addInput('clk', clk);
+
+    final intermediate =
+        LogicArray([4], 1, name: 'asdf', naming: Naming.mergeable);
+    final arrOut = ArraySubModOut(clk).arrOut;
+    for (var i = 0; i < intermediate.width; i++) {
+      final idx = (i + 1) % intermediate.width;
+      intermediate.elements[idx] <= arrOut.elements[idx];
+    }
+    ArraySubModIn(clk, intermediate);
+  }
+}
+
+class ArraySubModIn extends Module {
+  ArraySubModIn(Logic clk, LogicArray inp) {
+    clk = addInput('clk', clk);
+    addInputArray('inp', inp, dimensions: [4]);
+  }
+}
+
+class ArraySubModOut extends Module {
+  LogicArray get arrOut => output('arrOut') as LogicArray;
+  ArraySubModOut(Logic clk) {
+    clk = addInput('clk', clk);
+    addOutputArray('arrOut', dimensions: [4]);
+  }
+}
+
 class ArrayWithShuffledAssignment extends Module {
   ArrayWithShuffledAssignment(LogicArray a) {
     final inpA = addInputArray('a', a, dimensions: a.dimensions);
@@ -61,6 +93,24 @@ void main() {
   tearDown(() async {
     await Simulator.reset();
   });
+
+  test('simple 1d collapse', () async {
+    final mod = SimpleLAPassthrough(LogicArray([4], 1));
+    await mod.build();
+    final sv = mod.generateSynth();
+
+    expect(sv, contains('assign laOut = laIn;'));
+  });
+
+  test('array collapse for cross-module connection', () async {
+    final mod = ArrayTopMod(Logic());
+    await mod.build();
+    final sv = mod.generateSynth();
+
+    expect(sv, contains(RegExp(r'ArraySubModIn.*\.inp\(inp\)')));
+    expect(sv, contains(RegExp(r'ArraySubModOut.*\.arrOut\(inp\)')));
+  });
+
   test('array nets with intermediate collapse', () async {
     final mod = ArrayModuleWithNetIntermediates(
         LogicArray([3, 3], 1), LogicArray([3, 3], 1));