Skip to content

Commit

Permalink
Preparing to release v0.5.3
Browse files Browse the repository at this point in the history
  • Loading branch information
mkorbel1 committed Apr 5, 2024
1 parent 4329213 commit d1c79eb
Show file tree
Hide file tree
Showing 5 changed files with 40 additions and 2 deletions.
2 changes: 2 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -1,3 +1,5 @@
# NOTE: Be sure to update .pubignore as well!

# Files and directories created by pub
.dart_tool/
.packages
Expand Down
26 changes: 26 additions & 0 deletions .pubignore
Original file line number Diff line number Diff line change
@@ -0,0 +1,26 @@
# NOTE: Everything (probably) from .gitignore should be in here!

# Files and directories created by pub
.dart_tool/
.packages
pubspec.lock

# Conventional directory for build outputs
build/

# Directory created by dartdoc
doc/api/

# Other stuff
tmp_test/
*.sv
*.vcd
*_fsm.md
.vscode/*

# Exceptions
!.vscode/extensions.json
!test/example_icarus_waves.vcd

# Release with devtools build
!extension/devtools/build
10 changes: 10 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
@@ -1,3 +1,13 @@
## 0.5.3

- Added beta version of the ROHD DevTools Extension to aid in ROHD hardware debug by displaying module hierarchy and signal information visually and interactively (<https://github.com/intel/rohd/pull/435>).
- Added absolute value (`abs()`) to both `Logic` and `LogicValue` (<https://github.com/intel/rohd/pull/442>).
- Added `assignSubset` for performing an assignment on a subset of a `LogicArray` (<https://github.com/intel/rohd/pull/456>).
- Made conditional assignments more optimistic with partially invalid values (<https://github.com/intel/rohd/pull/459>).
- Upgraded the simulator to support cancelling actions and registering actions at the current time (<https://github.com/intel/rohd/pull/468>).
- Fixed a bug where SystemVerilog generation could mishandle naming collisions between `Logic`s and `LogicArray`s (<https://github.com/intel/rohd/pull/473>).
- Added new checks to help catch SystemVerilog generation issues in cases where built-in functionality is overridden.

## 0.5.2

- Added APIs for accessing indices of a `List<Logic>` using another `Logic`: `Logic.selectFrom` and `List<Logic>.selectIndex` (<https://github.com/intel/rohd/pull/438>).
Expand Down
2 changes: 1 addition & 1 deletion lib/src/utilities/config.dart
Original file line number Diff line number Diff line change
Expand Up @@ -10,5 +10,5 @@
/// A utility for ROHD configuration file.
class Config {
/// The version of the ROHD framework.
static const String version = '0.5.2';
static const String version = '0.5.3';
}
2 changes: 1 addition & 1 deletion pubspec.yaml
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
name: rohd
version: 0.5.2
version: 0.5.3
description: The Rapid Open Hardware Development (ROHD) framework, a framework for describing and verifying hardware.
homepage: https://intel.github.io/rohd-website
repository: https://github.com/intel/rohd
Expand Down

0 comments on commit d1c79eb

Please sign in to comment.