Preparing to release v0.3.0

intel · May 5, 2022 · 67ecc38 · 67ecc38
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,4 +1,4 @@
-## (next release)
+## 0.3.0
 - Breaking: Merged `LogicValue` and `LogicValues` into one type called `LogicValue`.
 - Deprecation: Aligned `LogicValue` to `Logic` by renaming `length` to `width`.
 - Breaking: `Logic.put` no longer accepts `List<LogicValue>`, swizzle it together instead.
@@ -14,6 +14,7 @@
 - Improved flexibility of `IfBlock`.
 - Added `withSet` on `LogicValue` and `Logic` to make it easier to assign subsets of signals and values (https://github.com/intel/rohd/issues/101).
 - Fixed a bug where 0-bit signals would sometimes improperly generate 0-bit constants in generated SystemVerilog (https://github.com/intel/rohd/issues/122).
+- Added capability to reserve instance names, as well as provide and reserve definition names, for `Module`s and their corresponding generated outputs.
 
 ## 0.2.0
 - Updated implementation to avoid `Iterable.forEach` to make debug easier.

diff --git a/pubspec.yaml b/pubspec.yaml
@@ -1,6 +1,6 @@
 name: rohd
 description: The Rapid Open Hardware Development (ROHD) framework, a framework for describing and verifying hardware
-version: 0.2.0
+version: 0.3.0
 homepage: https://github.com/intel/rohd
 repository: https://github.com/intel/rohd
 issue_tracker: https://github.com/intel/rohd/issues