Skip to content
This repository has been archived by the owner on Jan 26, 2025. It is now read-only.

Issues: hell03end/verilog-uart

4 Open 0 Closed
4 Open 0 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Collaborate invite
#5 opened Nov 8, 2022 by AhsanAliUet
Warning: This code does not work properly
#3 opened Nov 4, 2020 by AgnerF
3
control data width enhancement New feature or request help wanted Extra attention is needed
#2 opened Jun 3, 2018 by hell03end
add testbench help wanted Extra attention is needed
#1 opened Jun 3, 2018 by hell03end
ProTip! Follow long discussions with comments:>50.